Patents by Inventor Sunil Parthasarathy

Sunil Parthasarathy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7349230
    Abstract: Associative memory bit cells are disclosed for selectively producing binary or ternary content-addressable memory lookup results. Associative memory bit cells are grouped together to act as n binary content-addressable memory cells (CAM) bits or m ternary content-addressable memory (TCAM) bits, with n>m>0. Based on the programming of the associative memory bit cells and the selective application of search values (based on whether they are acting as CAM or TCAM bit cells), the appropriate determination is made as to whether or not to signal a hit or a miss based on the current input search values. These associative memory bit cells can also be combined to provide error protection for either of their operating modes. Error protection can be used to enable a correct result when e bit errors occur in the stored values in the associative memory bit cells.
    Type: Grant
    Filed: August 2, 2006
    Date of Patent: March 25, 2008
    Assignee: Cisco Technology, Inc.
    Inventors: Sunil Parthasarathy, Sriram Chitoor Krishnan
  • Patent number: 7345897
    Abstract: Ternary content-addressable memory (TCAM) entries are disclosed for use in performing error-protected lookup operations by allowing an error budget of u deviations in values stored in each entry. Each TCAM entry is configured to identify a hit condition (else a miss condition) with an input lookup word if its stored value matches each bit of the lookup word with the exception of zero to u of its cells not matching. This determination may be made, for example, using discrete logic or based a voltage level of one or more match lines. Furthermore, it is possible to store at least 2u+1 copies of a data value desired to be protected in a such a TCAM entry among its said t TCAM cells.
    Type: Grant
    Filed: June 1, 2006
    Date of Patent: March 18, 2008
    Assignee: Cisco Technology, Inc.
    Inventors: Sriram Chitoor Krishnan, Rina Panigrahy, Sunil Parthasarathy
  • Patent number: 7266004
    Abstract: A content-addressable memory entry is identified as being matched if it matches all bit positions of a lookup word or does not match for less than a predetermined number of bit positions. A match line of the content-addressable memory entry is precharged. During a subsequent matching phase, each of the bit positions of the content-addressable memory entry provides a discharge path for the precharged match line. Whether or not the content-addressable memory should be identified as being matched is then determined typically by comparing the match reference voltage of the match line to a predetermined voltage level at a predetermined time, with the predetermined voltage level and predetermined time selected for the allowed number of bit positions that do not have to be matched while still considering the content-addressable memory entry to have been matched, and the implementation technology of the embodiment.
    Type: Grant
    Filed: October 18, 2005
    Date of Patent: September 4, 2007
    Assignee: Cisco Technology, Inc.
    Inventors: Sriram Chitoor Krishnan, Sunil Parthasarathy
  • Publication number: 20070086227
    Abstract: Ternary content-addressable memory (TCAM) entries are disclosed for use in performing error-protected lookup operations by allowing an error budget of u deviations in values stored in each entry. Each TCAM entry is configured to identify a hit condition (else a miss condition) with an input lookup word if its stored value matches each bit of the lookup word with the exception of zero to u of its cells not matching. This determination may be made, for example, using discrete logic or based a voltage level of one or more match lines. Furthermore, it is possible to store at least 2u+1 copies of a data value desired to be protected in a such a TCAM entry among its said t TCAM cells.
    Type: Application
    Filed: June 1, 2006
    Publication date: April 19, 2007
    Applicant: CISCO TECHNOLOGY, INC., A CALIFORNIA CORPORATION
    Inventors: Sriram Krishnan, Rina Panigrahy, Sunil Parthasarathy
  • Publication number: 20070088909
    Abstract: A content-addressable memory entry is identified as being matched if it matches all bit positions of a lookup word or does not match for less than a predetermined number of bit positions. A match line of the content-addressable memory entry is precharged. During a subsequent matching phase, each of the bit positions of the content-addressable memory entry provides a discharge path for the precharged match line. Whether or not the content-addressable memory should be identified as being matched is then determined typically by comparing the match reference voltage of the match line to a predetermined voltage level at a predetermined time, with the predetermined voltage level and predetermined time selected for the allowed number of bit positions that do not have to be matched while still considering the content-addressable memory entry to have been matched, and the implementation technology of the embodiment.
    Type: Application
    Filed: October 18, 2005
    Publication date: April 19, 2007
    Applicant: CISCO TECHNOLOGY, INC., A CALIFORNIA CORPORATION
    Inventors: Sriram Chitoor Krishnan, Sunil Parthasarathy
  • Publication number: 20070088910
    Abstract: Associative memory bit cells are disclosed for selectively producing binary or ternary content-addressable memory lookup results. Associative memory bit cells are grouped together to act as n binary content-addressable memory cells (CAM) bits or m ternary content-addressable memory (TCAM) bits, with n>m>0. Based on the programming of the associative memory bit cells and the selective application of search values (based on whether they are acting as CAM or TCAM bit cells), the appropriate determination is made as to whether or not to signal a hit or a miss based on the current input search values. These associative memory bit cells can also be combined to provide error protection for either of their operating modes. Error protection can be used to enable a correct result when e bit errors occur in the stored values in the associative memory bit cells.
    Type: Application
    Filed: August 2, 2006
    Publication date: April 19, 2007
    Applicant: CISCO TECHNOLOGY, INC., A CALIFORNIA CORPORATION
    Inventors: Sunil Parthasarathy, Sriram Krishnan