Patents by Inventor Sunil Rajan
Sunil Rajan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11909853Abstract: Methods and systems for calibrating clock skew in a SerDes receiver. A method includes detecting a skew in a clock with respect to an edge of a reference clock, based on a value sampled by the clock and a value sampled by the reference clock at an edge of a data pattern, for a first Phase Interpolator (PI) code; determining a count of the skew from a de-serialized data word including outcome values obtained based on values sampled by the clock and values sampled by the reference clock at a predefined number of edges of the data pattern; obtaining a skew calibration code corresponding to the first PI code, from a binary variable obtained by accumulating an encoded variable to a previously generated binary variable; and calibrating the skew by performing a positive phase shift or a negative phase shift to the clock based on the skew calibration code.Type: GrantFiled: March 16, 2022Date of Patent: February 20, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Saikat Hazra, Avneesh Singh Verma, Raghavendra Molthati, Sunil Rajan, Tamal Das, Ankit Garg, Praveen S Bharadwaj, Sanjeeb Kumar Ghosh
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Patent number: 11906585Abstract: Built-in-self-test (BIST operations are performed by receiver lanes of a multilane receiver system, wherein at least one receiver lane is configured as a synthesized clock source for other receiver lanes configured to perform BIST operations. The at least one receiver lane configured as the synthesized clock source may generate a clock signal and provide the clock signal to the other receiver lanes performing the BIST operations. In some examples, digital control signals may be used for coordinating the enablement of the at least one receiver lane to function as the synthesized clock source and for coordinating the enablement of the other receiver lanes to perform BIST operations.Type: GrantFiled: April 1, 2022Date of Patent: February 20, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: A Santosh Kumar Reddy, Gunjan Mandal, Parin Rajnikant Bhuta, Raghavendra Molthati, Saikat Hazra, Sanjeeb Kumar Ghosh, Sunil Rajan, Krupal Jitendra Mehta, Praveen S Bharadwaj
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Publication number: 20240044978Abstract: Methods and systems for determining and calibrating non-linearity in a phase interpolator. Embodiments determine a first jitter value that causes the bit error rate (BER) of a data sequence to exceed a predefined target BER, when a recovered clock is aligned with the data sequence at a first PI code. The recovered clock is obtained from a data pattern representing the data sequence. Embodiments determine a second jitter value that causes the BER of the data sequence to exceed the predefined target BER at a second PI code. The first PI code may immediately precede or succeed the second PI code. Embodiments determine a Differential Non-Linearity (DNL) corresponding to the second PI code, based on a phase shift introduced to the recovered clock by the second PI code relative to the first PI code, the first jitter value, and the second jitter value. All DNL values corresponding to all PI codes may be determined in a similar manner.Type: ApplicationFiled: July 7, 2023Publication date: February 8, 2024Inventors: Gunjan Mandal, Sunil Rajan, Raghavendra Molthati
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Publication number: 20230198732Abstract: Methods and systems for calibrating clock skew in a SerDes receiver. A method includes detecting a skew in a clock with respect to an edge of a reference clock, based on a value sampled by the clock and a value sampled by the reference clock at an edge of a data pattern, for a first Phase Interpolator (PI) code; determining a count of the skew from a de-serialized data word including outcome values obtained based on values sampled by the clock and values sampled by the reference clock at a predefined number of edges of the data pattern; obtaining a skew calibration code corresponding to the first PI code, from a binary variable obtained by accumulating an encoded variable to a previously generated binary variable; and calibrating the skew by performing a positive phase shift or a negative phase shift to the clock based on the skew calibration code.Type: ApplicationFiled: March 16, 2022Publication date: June 22, 2023Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Saikat HAZRA, Avneesh Singh VERMA, Raghavendra MOLTHATI, Sunil RAJAN, Tamal DAS, Ankit GARG, Praveen S. BHARADWAJ, Sanjeeb Kumar GHOSH
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Publication number: 20230194608Abstract: The present disclosure provides systems and methods for performing built-in-self-test (BIST) operations without a dedicated clock source. The BIST operations are performed by receiver lanes of a multilane receiver system, wherein at least one receiver lane is configured as synthesized clock source for other receiver lanes configured to perform BIST operations. The at least one receiver lane configured as the synthesized clock source may generate a clock signal and provide the clock signal to the other receiver lanes performing the BIST operations. In some examples, digital control signals may be used for coordinating the enablement of the at least one receiver lane to function as the synthesized clock source and for coordinating the enablement of the other receiver lanes to perform BIST operations.Type: ApplicationFiled: April 1, 2022Publication date: June 22, 2023Inventors: A Santosh Kumar Reddy, Gunjan Mandal, Parin Rajnikant Bhuta, Raghavendra Molthati, Saikat Hazra, Sanjeeb Kumar Ghosh, Sunil Rajan, Krupal Jitendra Mehta, Praveen S. Bharadwaj
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Patent number: 10951441Abstract: An Alternating Current (AC) and Direct Current (DC) coupled electronic receiver system including a receiver, an AC-coupling capacitor between an input of the receiver system and the receiver, a bypass switch configured to selectively bypass the AC-coupling capacitor to DC-couple the input to the receiver, a bypass switch driving circuit configured to cause the bypass switch to switch ‘ON’ and thereby DC-couple the input to the receiver, and cause the bypass switch to switch ‘OFF’ and thereby AC-couple the input to the receiver, and a voltage-following transistor between a source and a gate of the bypass switch configured to maintain an ‘OFF’ state of the bypass switch while the input is AC-coupled.Type: GrantFiled: August 12, 2019Date of Patent: March 16, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: A Santosh Kumar Reddy, Sumanth Chakkirala, Sunil Rajan
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Publication number: 20200403828Abstract: An Alternating Current (AC) and Direct Current (DC) coupled electronic receiver system including a receiver, an AC-coupling capacitor between an input of the receiver system and the receiver, a bypass switch configured to selectively bypass the AC-coupling capacitor to DC-couple the input to the receiver, a bypass switch driving circuit configured to cause the bypass switch to switch ‘ON’ and thereby DC-couple the input to the receiver, and cause the bypass switch to switch ‘OFF’ and thereby AC-couple the input to the receiver, and a voltage-following transistor between a source and a gate of the bypass switch configured to maintain an ‘OFF’ state of the bypass switch while the input is AC-coupled.Type: ApplicationFiled: August 12, 2019Publication date: December 24, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: A Santosh Kumar REDDY, Sumanth CHAKKIRALA, Sunil RAJAN
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Patent number: 8659362Abstract: A relaxation oscillator circuit with reduced sensitivity of oscillation frequency to comparator delay variation includes a first current source that generates charging current, a second current source coupled to the first current source to generate reference voltage, a resistor coupled to the second current source to enable generation of the reference voltage, a capacitor coupled to the first current source that is charged based on the charging current, a comparator responsive to voltage corresponding to the capacitor and the reference voltage to generate output voltage, a peak detector coupled to the capacitor to generate peak voltage, an error detector coupled to the peak detector and the second current source to generate an error based on the peak voltage and the reference voltage, and a controller coupled to the error detector to control one of the charging current, offset voltage input to the comparator, and capacitance of the capacitor.Type: GrantFiled: November 22, 2011Date of Patent: February 25, 2014Assignee: Cadence AMS Design India Private LimitedInventors: Prasenjit Bhowmik, Rishi Mathur, Sriram Ganesan, Sunil Rajan
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Publication number: 20120319789Abstract: A relaxation oscillator circuit with reduced sensitivity of oscillation frequency to comparator delay variation includes a first current source that generates charging current, a second current source coupled to the first current source to generate reference voltage, a resistor coupled to the second current source to enable generation of the reference voltage, a capacitor coupled to the first current source that is charged based on the charging current, a comparator responsive to voltage corresponding to the capacitor and the reference voltage to generate output voltage, a peak detector coupled to the capacitor to generate peak voltage, an error detector coupled to the peak detector and the second current source to generate an error based on the peak voltage and the reference voltage, and a controller coupled to the error detector to control one of the charging current, offset voltage input to the comparator, and capacitance of the capacitor.Type: ApplicationFiled: November 22, 2011Publication date: December 20, 2012Applicant: Cosmic Circuits Private LimitedInventors: Prasenjit Bhowmik, Rishi Mathur, Sriram Ganesan, Sunil Rajan