Patents by Inventor Sunil Thomas
Sunil Thomas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20110117130Abstract: The present invention provides an isolated and purified heat shock protein 60 (Hsp60) peptide having the amino acid sequence of SEQ ID NO:2. The instant invention is also directed to a vaccine against Ehrlichia comprising a peptide homologous to the amino acid sequence of SEQ ID NO:2. The instant invention is also directed to an antibody directed against a peptide homologous to the amino acid sequence of SEQ ID NO:2. The instant invention is also directed to a method of determining whether a subject is infected with Ehrlichia, comprising the steps of: contacting a sample from a subject with the antibody described herein; and detecting a resulting antibody reaction, wherein a positive reaction indicates the subject is infected with Ehrlichia.Type: ApplicationFiled: November 10, 2010Publication date: May 19, 2011Inventors: David H. Walker, Sunil Thomas
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Patent number: 7763975Abstract: A low-cost ceramic package, in land-grid array or ball-grid array configuration, for micromechanical components is fabricated by coating the whole integrated circuits wafer with a protective material, selectively etching the coating for solder ball attachment, singulating the chips, flip-chip assembling a chip onto the opening of a ceramic substrate, under filling the gaps between the solder joints with a polymeric encapsulant, removing the protective material form the components, and attaching a lid to the substrate for sealing the package. It is an aspect of the present invention to be applicable to a variety of different semiconductor micromechanical devices, for instance actuators, motors, sensors, spatial light modulators, and deformable mirror devices. In all applications, the invention achieves technical advantages as well as significant cost reduction and yield increase.Type: GrantFiled: December 21, 2007Date of Patent: July 27, 2010Assignee: Texas Instruments IncorporatedInventor: Sunil Thomas
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Patent number: 7553690Abstract: This disclosure is concerned with starved source diffusion methods for forming avalanche photodiodes are provided for controlling an edge effect. In one example, a method for manufacturing an avalanche photodiode includes forming an absorber layer and an avalanche layer over a substrate. Next, a patterned mask defining one or more openings is formed over a surface of the avalanche layer. Finally, a dopant is deposited over the patterned mask and the avalanche layer such that the dopant is blocked by the patterned mask but diffuses into the avalanche layer in areas where the patterned mask defines an opening. The patterned mask is configured such that the depth to which the dopant diffuses into the avalanche layer varies so as to form a sloped diffusion front in the avalanche layer.Type: GrantFiled: June 14, 2005Date of Patent: June 30, 2009Assignee: Finisar CorporationInventors: Daniel Francis, Rashit Nabiev, Richard P. Ratowsky, David Bruce Young, Sunil Thomas, Roman Dimitrov
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Publication number: 20080093689Abstract: A low-cost ceramic package, in land-grid array or ball-grid array configuration, for micromechanical components is fabricated by coating the whole integrated circuits wafer with a protective material, selectively etching the coating for solder ball attachment, singulating the chips, flip-chip assembling a chip onto the opening of a ceramic substrate, underfilling the gaps between the solder joints with a polymeric encapsulant, removing the protective material form the components, and attaching a lid to the substrate for sealing the package. It is an aspect of the present invention to be applicable to a variety of different semiconductor micromechanical devices, for instance actuators, motors, sensors, spatial light modulators, and deformable mirror devices. In all applications, the invention achieves technical advantages as well as significant cost reduction and yield increase.Type: ApplicationFiled: December 21, 2007Publication date: April 24, 2008Applicant: TEXAS INSTRUMENTS INCORPORATEDInventor: Sunil Thomas
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Publication number: 20060121683Abstract: Systems and methods for controlling edge gain in avalanche photodiodes. During fabrication of an avalanche photodiode, the photodiode is diffused with a dopant. The mask used for the dopant includes a plurality of openings such that the dopant diffuses within the photodiode to create a plurality of interconnected spheres. The diffusion front has a shape to introduce an edge effect into the center of the photodiode. The diffusion front ameliorates the edge effect by introducing the edge effect into the center of the photodiode.Type: ApplicationFiled: December 8, 2004Publication date: June 8, 2006Inventors: Daniel Francis, Richard Ratowsky, Ashish Verma, Sunil Thomas, Roman Dimitrov
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Publication number: 20060084187Abstract: This disclosure is concerned with starved source diffusion methods for forming avalanche photodiodes are provided for controlling an edge effect. In one example, a method for manufacturing an avalanche photodiode includes forming an absorber layer and an avalanche layer over a substrate. Next, a patterned mask defining one or more openings is formed over a surface of the avalanche layer. Finally, a dopant is deposited over the patterned mask and the avalanche layer such that the dopant is blocked by the patterned mask but diffuses into the avalanche layer in areas where the patterned mask defines an opening. The patterned mask is configured such that the depth to which the dopant diffuses into the avalanche layer varies so as to form a sloped diffusion front in the avalanche layer.Type: ApplicationFiled: June 14, 2005Publication date: April 20, 2006Inventors: Daniel Francis, Rashit Nabiev, Richard Ratowsky, David Young, Sunil Thomas, Roman Dimitrov
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Publication number: 20060081874Abstract: Starved source diffusion methods for forming avalanche photodiodes (APDs) are provided for controlling the edge effect. The edge effect is controlled by reducing edge gain near the edges of an APD active region. This is accomplished by creating a sloped diffusion front near the edges of the active region. The sloped diffusion front is advantageously formed in a single doping step by using a patterned mask during doping. The patterned mask reduces the depth to which dopants diffuse in areas where it only partly covers the underlying layer. By covering more of the underlying layer nearer the edge and progressively less towards the center, the sloped diffusion front is formed. The shallower diffusion depth near the edge reduces the edge gain, and therefore the edge effect. As a result, an APD to fiber misalignment is less likely, and possibility of edge breakdown is greatly reduced.Type: ApplicationFiled: October 15, 2004Publication date: April 20, 2006Inventors: Daniel Francis, Rashit Nabiev, Richard Ratowsky, David Young, Sunil Thomas, Roman Dimitrov
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Publication number: 20040084738Abstract: A low-cost ceramic package, in land-grid array or ball-grid array configuration, for micromechanical components is fabricated by coating the whole integrated circuits wafer with a protective material, selectively etching the coating for solder ball attachment, singulating the chips, flip-chip assembling a chip onto the opening of a ceramic substrate, underfilling the gaps between the solder joints with a polymeric encapsulant, removing the protective material form the components, and attaching a lid to the substrate for sealing the package.Type: ApplicationFiled: October 28, 2003Publication date: May 6, 2004Inventor: Sunil Thomas
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Patent number: 6656768Abstract: A low-cost ceramic package, in land-grid array or ball-grid array configuration, for micromechanical components is fabricated by coating the whole integrated circuits wafer with a protective material, selectively etching the coating for solder ball attachment, singulating the chips, flip-chip assembling a chip onto the opening of a ceramic substrate, underfilling the gaps between the solder joints with a polymeric encapsulant, removing the protective material form the components, and attaching a lid to the substrate for sealing the package. It is an aspect of the present invention to be applicable to a variety of different semiconductor micromechanical devices, for instance actuators, motors, sensors, spatial light modulators, and deformable mirror devices. In all applications, the invention achieves technical advantages as well as significant cost reduction and yield increase.Type: GrantFiled: October 30, 2002Date of Patent: December 2, 2003Assignee: Texas Instruments IncorporatedInventor: Sunil Thomas
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Publication number: 20030052404Abstract: A low-cost ceramic package, in land-grid array or ball-grid array configuration, for micromechanical components is fabricated by coating the whole integrated circuits wafer with a protective material, selectively etching the coating for solder ball attachment, singulating the chips, flip-chip assembling a chip onto the opening of a ceramic substrate, underfilling the gaps between the solder joints with a polymeric encapsulant, removing the protective material form the components, and attaching a lid to the substrate for sealing the package.Type: ApplicationFiled: October 30, 2002Publication date: March 20, 2003Inventor: Sunil Thomas
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Patent number: 6507082Abstract: A low-cost ceramic package, in land-grid array or ball-grid array configuration, for micromechanical components is fabricated by coating the whole integrated circuits wafer with a protective material, selectively etching the coating for solder ball attachment, singulating the chips, flip-chip assembling a chip onto the opening of a ceramic substrate, underfilling the gaps between the solder joints with a polymeric encapsulant, removing the protective material form the components, and attaching a lid to the substrate for sealing the package. It is an aspect of the present invention to be applicable to a variety of different semiconductor micromechanical devices, for instance actuators, motors, sensors, spatial light modulators, and deformable mirror devices. In all applications, the invention achieves technical advantages as well as significant cost reduction and yield increase.Type: GrantFiled: February 8, 2001Date of Patent: January 14, 2003Assignee: Texas Instruments IncorporatedInventor: Sunil Thomas
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Publication number: 20020163055Abstract: A low-cost ceramic package, in land-grid array or ball-grid array configuration, for micromechanical components is fabricated by coating the whole integrated circuits wafer with a protective material, selectively etching the coating for solder ball attachment, singulating the chips, flip-chip assembling a chip onto the opening of a ceramic substrate, underfilling the gaps between the solder joints with a polymeric encapsulant, removing the protective material form the components, and attaching a lid to the substrate for sealing the package.Type: ApplicationFiled: February 8, 2001Publication date: November 7, 2002Inventor: Sunil Thomas
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Patent number: 6230399Abstract: A TAB device (10) is coupled to a circuit board (12). The TAB device (10) includes a semiconductor die (11) having leads (18) extending therefrom. A material layer (30), typically a polyimide layer, covers the inward portion of the leads (18) to maintain leading position during attachment of the TAB device (10) to the circuit board (12). Prior to attachment, a backside encapsulation region (40) is applied to the backside of the TAB device (10), sealing the backside of the leads (18). The backside encapsulation material is selected to have a coefficient of thermal expansion similar to the coefficient of thermal expansion of the first material layer (18). The backside encapsulation material is selected to have a coefficient of thermal expansion similar to the coefficient of thermal expansion of the first material layer (30), to prevent excessive warpage.Type: GrantFiled: August 12, 1998Date of Patent: May 15, 2001Assignee: Texas Instruments IncorporatedInventors: Abhay Maheshwari, Sunil Thomas
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Patent number: 6228680Abstract: A semiconductor assembly and method of fabrication comprising an integrated circuit chip, an electrically insulating substrate, a multitude of solder balls for interconnecting both parts while spacing them apart by a gap, and a polymeric encapsulant filling the gap. The method of fabrication includes heating and cooling cycles, based on stress modeling, such that all mechanical stress levels in the dielectric layers of the circuit chip and in the solder balls are reduced to levels safe for operating the semiconductor assembly.Type: GrantFiled: May 1, 1999Date of Patent: May 8, 2001Assignee: Texas Instruments IncorporatedInventor: Sunil Thomas
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Patent number: 6213347Abstract: An apparatus for the fabrication of a semiconductor assembly and a method of underfilling flip-chip devices are disclosed. The apparatus for multiple controlled dispensing of polymeric precursors filled with silica and anhydrides comprises a center feed tube supplying the proecursor; a header connecting the center tube to a plurality of distribution tubes, whereby the distribution tubes acquire predetermined distances from the center tube; a nozzle at the end of each distribution tube; and these nozzles having increasingly larger cross sections, the farther the respective distribution tube is positioned from the center tube, whereby the dispense rate of the precursor remains the same for all distribution tubes.Type: GrantFiled: April 30, 1999Date of Patent: April 10, 2001Assignee: Texas Instruments IncorporatedInventor: Sunil Thomas
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Patent number: 6097099Abstract: A design having a semiconductor microchip bonded to a circuit board is described. This design may include: a printed circuit board (58); a semiconductor microchip (56) bonded to the circuit board (58) by means of an adhesive layer placed between the bonding surface of the microchip (56) and the desired bonding site on the circuit board (58); the adhesive layer providing for thermal relief as well as electrical contact between the microchip (56) and circuit board (58), and consisting of two or more concentric regions that adjoin but do not overlap one another; one being a center core region (50) of thermally and electrically conductive material; the other being a perimeter region (54) of thermally conductive and electrically nonconductive material surrounding the center core region (50) such that the perimeter region's (54) inner boundary completely bounds the center core region (50); and such that the perimeter region's (54) outer boundary extends to a lead on the microchip (56).Type: GrantFiled: October 15, 1997Date of Patent: August 1, 2000Assignee: Texas Instruments IncorporatedInventors: Prosenjit Ghosh, Sunil Thomas
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Patent number: 6090641Abstract: A design having a semiconductor microchip bonded to a circuit board is described. This design may include: a printed circuit board (58); a semiconductor microchip (56) bonded to the circuit board (58) by means of an adhesive layer placed between the bonding surface of the microchip (56) and the desired bonding site on the circuit board (58); the adhesive layer providing for thermal relief as well as electrical contact between the microchip (56) and circuit board (58), and consisting of two or more concentric regions that adjoin but do not overlap one another; one being a center core region (50) of thermally and electrically conductive material; the other being a perimeter region (54) of thermally conductive and electrically nonconductive material surrounding the center core region (50) such that the perimeter region's (54) inner boundary completely bounds the center core region (50), and such that the perimeter region's (54) outer boundary extends to a lead on the microchip (56).Type: GrantFiled: January 20, 1998Date of Patent: July 18, 2000Assignee: Texas Instruments IncorporatedInventors: Prosenjit Ghosh, Sunil Thomas
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Patent number: 5834336Abstract: A TAB device (10) is coupled to a circuit board (12). The TAB device (10) includes a semiconductor die (11) having leads (18) extending therefrom. A material layer (30), typically a polyimide layer, covers the inward portion of the leads (18) to maintain leading position during attachment of the TAB device (10) to the circuit board (12). Prior to attachment, a backside encapsulation region (40) is applied to the backside of the TAB device (10), sealing the backside of the leads (18). The backside encapsulation material is selected to have a coefficient of thermal expansion similar to the coefficient of thermal expansion of the first material layer (18). The backside encapsulation material is selected to have a coefficient of thermal expansion similar to the coefficient of thermal expansion of the first material layer (30), to prevent excessive warpage.Type: GrantFiled: March 12, 1996Date of Patent: November 10, 1998Assignee: Texas Instruments IncorporatedInventors: Abhay Maheshwari, Sunil Thomas
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Patent number: 5811317Abstract: A method for assembly of bare silicon die onto flexible or thin laminate substrates that minimizes substrate and die warpage induced after underfill cure operations and at the same time reduces the cycle time for the assembly process. More specifically, an opposing layer of thermoset component is adhered to a balance plate (metal) or other material with applicable coefficient of thermal expansion "CTE" and modulus of elasticity on the top of the die. The offsetting layer of material causes the die to warp to the other side and as a result the two self opposing warpage effects neutralize themselves.Type: GrantFiled: August 25, 1995Date of Patent: September 22, 1998Assignee: Texas Instruments IncorporatedInventors: Abhay Maheshwari, Sunil Thomas, Chris Thornton
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Patent number: 5745985Abstract: A method of attaching a microchip onto a circuit board is described. The method may include: forming a core portion of thermally conductive and electrically conductive material 50; forming a perimeter portion of thermally conductive and electrically nonconductive material 54; placing the core portion of thermally conductive and electrically conductive material 50 at a site on a circuit board 58 where the microchip 56 will be bonded; placing the perimeter portion of thermally conductive and electrically non-conductive material 54 around the core portion 50 on the circuit board; and attaching microchip component 56 to the core portion 50 and the perimeter portion 54. The method may also include applying a catalyst on the circuit board before attaching the core and perimeter portions. The method may also include curing the core portion and the perimeter portion at 90 degrees C. for 10 minutes and then applying a catalyst on the core portion and the perimeter portion.Type: GrantFiled: October 20, 1995Date of Patent: May 5, 1998Assignee: Texas Instruments IncorporatedInventors: Prosenjit Ghosh, Sunil Thomas