Abstract: Network data is received in a first format. The data is converted to a synchronous optical network (SONET) format. Switching functions are performed on the SONET formatted data. The SONET formatted data is converted to a second format. In one embodiment, the switching functions on the SONET formatted data contains performing time switching and space switching.

Abstract: Multiple streams of bits are received. One or more bits are selected from a stream of bits based, at least in part, on a space control register value and a time control register value. In one embodiment, a time control register stores a value indicating a selected bit from a sequence of bits, a counter counts bits in the sequence of bits from a predetermined bit, and a comparator is coupled to the time control register and to the counter to generate a load signal when a value stored in the time control register and a value provided by the counter are equal. The load signal causes the latch to load a value output by the multiplexer.

Abstract: A plurality of transmission circuits transmit data over one or more output lines. A plurality of receiving circuits receive data over one or more of a set of input lines A plurality of parallel-serial conversion circuits coupled to the plurality of transmission circuits and to the plurality of receiving circuits, the plurality of conversion circuits to convert parallel signals to one or more sets of serial signals and to send the converted serial signals to one or more corresponding transmission circuits, and to receive one or more sets of serial signals from one or more of the receiving circuits and to convert the serial signals to parallel signals.

Abstract: Methods and apparatuses for laying out an integrated circuit include a first plurality of I/O ports that are positioned along the first side, a plurality of queues that are coupled to the first plurality of I/O ports, a first bus that is positioned extending from the plurality of queues toward the second side to couple a control circuit to the plurality of queues, second plurality of I/O ports that are positioned along the third side and the fourth side, and a second bus that is positioned between the control circuit and the second plurality of I/O ports to couple the control circuit to the second plurality of I/O ports, wherein the first bus and the second bus are positioned such that the respective bus lines do not cross over each other. A time and space switching apparatus and component cell permit a bit within a data line to be selected.

Abstract: An electronic system includes a backplane, a first plurality of slots coupled to the backplane, the first plurality of slots having a first electrical interface to be coupled to electrical circuit cards of a first type, wherein the electrical circuit cards of the first type receive network data and convert the network data to SONET formatted data, and a second plurality of slots coupled to the backplane, the second plurality of slots having a second electrical interface to electrical circuit cards of a second type. The backplane routes data signals between the first plurality of slots and the second plurality of slots.

Abstract: A serial data signal having a predetermined sequence to indicate a start of a frame of data is received. The serial data signal is compared to a plurality of values. The plurality of values include the predetermined sequence and one or more values representing logical rotations of the predetermined sequence. A match signal is generated in response to the serial data signal matching one of the plurality of values.

Abstract: A clock signal is received. A synchronization signal is compared to the clock signal to determine whether the synchronization signal is asserted within a predetermined period of time with respect to clock signal cycles. The synchronization signal assertion is used to synchronize a circuit to an external event, if the synchronization signal assertion is received within the predetermined period of time. If the synchronization signal assertion is not received within the predetermined period of time the circuit is not synchronized.