Abstract: A superscaler processor capable of executing multiple instructions concurrently. The processor includes a program counter which identifies instructions for execution by multiple execution units. Further included is a register file made up of multiple register window pointer selects one of the multiple register windows. In response to the value of the current window pointer, a return prediction table provides a speculative program counter value, indicative of a return address of an instruction for a subroutine, corresponding to the selected register window. A watchpoint register stores the speculative program counter value. A fetch program counter, in response to the speculative program counter value, stores the instructions for execution after they have been identified by the program counter.

Abstract: A method and apparatus accepts a relative control transfer instruction and generates a compact absolute control transfer instruction which may have a number of bits one greater than the relative control transfer instruction and including flags to rapidly construct the target address of the relative control transfer instruction. The compact absolute control transfer instruction is generated by sign extending the displacement of the relative control transfer instructions and adding it to a set of least significant bits from the control transfer instruction address, and optionally coupling some or all of the bits from the result with the original opcode or a different opcode.

Abstract: A clocked instruction flow is managed subject to issue and fetch constraints through a plurality of instruction latches which receive instructions from selected memory locations. By checking the number of instructions fetched and issued, the fetch program counter is adjusted responsive to the status of selected state variables indicating instructions issued and fetched. The instruction latches are fully scheduled from cycle to cycle with instructions, by fetching instructions in accordance with a fetch program counter.

Abstract: An improved semiconductor device interconnect comprising a conductive layer (30) with an underlying diffusion barrier metal (26) is attached to a doped glass layer (20) by an intermediate metal adhesion layer (22). The metal adhesion layer (22) is deposited onto the doped glass layer (30) prior to the formation of contact openings (24) in the doped glass layer (30) and the subsequent formation of the interconnect metallization. In one embodiment, a titanium diffusion barrier (26) is deposited onto a doped glass layer (30) having an aluminum metal adhesion layer (22) thereon and contact openings (24) therethrough. The titanium is annealed to form a silicide (28) in a substrate region (14) exposed by the contact opening (24) and an aluminum interconnect (32) is formed contacting the silicide region (28).