Abstract: A phase accumulation digital-to-analog converter (DAC) is provided. A digital-to-time converter (DTC), including a reference clock chain with N number of series connected delay elements, accepts a clock signal with a leading clock edge and supplies a set signal representing a first delay of the leading clock edge. A data clock chain including N number of series connected accumulators, accepts the clock signal with the leading clock edge, accepts a binary coded digital word, and supplies a reset signal representing a second delay of the leading clock edge, responsive to the digital word. A phase-to-time logic (PTL) receives the set and reset signals and supplies a DTC output signal representing the difference in delay between the set and reset signals. A time-to-voltage converter (TVC) charges a load capacitor every clock period in response to the DTC output signal to supply an analog output signal.