Abstract: A method for manufacturing a semiconductor device is provided. The method includes: providing a lower channel pattern, an intermediate insulating pattern, and an upper channel pattern, which are stacked sequentially on a substrate along a vertical direction; forming a lower source/drain pattern connected to the lower channel pattern; forming an upper source/drain pattern connected to the upper channel pattern; forming a gate structure which surrounds the lower channel pattern and the upper channel pattern; forming a contact hole extending into the upper source/drain pattern and the lower source/drain pattern; forming a contact film in the contact hole; and performing an annealing process on the contact film to form a front source/drain contact.

Abstract: There is provided a semiconductor device capable of capable of improving element performance and reliability. A semiconductor device includes a lower conductive pattern disposed on a substrate, an upper conductive pattern disposed on the lower conductive pattern, and a first plug pattern disposed between the lower conductive pattern and the upper conductive pattern and connected to the lower conductive pattern and the upper conductive pattern. The first plug pattern includes a first barrier pattern that defines a first plug recess and a first plug metal pattern that fills the first plug recess, and the first plug metal pattern includes a first molybdenum pattern and a first tungsten pattern disposed on the first molybdenum pattern.

Abstract: A semiconductor memory device includes a bitline extending in a first direction; a first channel pattern on an upper surface of the bitline; a second channel pattern on the upper surface of the bitline; a first wordline extending in a second direction; a second wordline extending in the second direction; a first capacitor and a second capacitor connected to the first channel pattern and the second channel pattern, respectively; a first gate insulating pattern; a second gate insulating pattern ; a first ruthenium structure between the first channel pattern and the first capacitor; and a second ruthenium structure between the second channel pattern and the second capacitor, wherein an uppermost surface of the first gate insulating pattern is provided without the first ruthenium structure provided thereon, and an uppermost surface of the second gate insulating pattern is provided without the second ruthenium structure provided thereon.

Abstract: A semiconductor memory device semiconductor memory device includes a substrate, a plurality of wordlines stacked in a first direction on the substrate, channel regions between adjacent wordlines in the first direction and extending in a second direction, first source/drain regions on first sides of the channel regions, second source/drain regions on second sides of the channel regions, bitlines extending in the first direction on the substrate and connected to corresponding ones of the first source/drain regions, respectively, data storage elements connected to the second source/drain regions, respectively, and capping films between the second source/drain regions and corresponding ones of the data storage elements, respectively, the capping filing including insertion holes, respectively, wherein at least portions of the second source/drain regions are inserted into corresponding ones of the insertion holes of the capping films, respectively.

Abstract: There is provided a semiconductor device capable of capable of improving element performance and reliability. A semiconductor device includes a lower conductive pattern disposed on a substrate, an upper conductive pattern disposed on the lower conductive pattern, and a first plug pattern disposed between the lower conductive pattern and the upper conductive pattern and connected to the lower conductive pattern and the upper conductive pattern. The first plug pattern includes a first barrier pattern that defines a first plug recess and a first plug metal pattern that fills the first plug recess, and the first plug metal pattern includes a first molybdenum pattern and a first tungsten pattern disposed on the first molybdenum pattern.

Abstract: A semiconductor device includes a substrate including a first region, and a second region, a first gate structure and a second gate structure on the substrate of the first region, a third gate structure and a fourth gate structure on the substrate of the second region, a first interlayer insulating film on the substrate of the first region and including a first lower interlayer insulating film and a first upper interlayer insulating film, a second interlayer insulating film on the substrate of the second region and including a second lower interlayer insulating film and a second upper interlayer insulating film, a first contact between the first gate structure and the second gate structure and within the first interlayer insulating film, and a second contact formed between the third gate structure and the fourth gate structure and within the second interlayer insulating film.

Abstract: A display device may include: a first data line electrically connected to a first thin film transistor; a first pixel electrode electrically connected with the first thin film transistor; a second data line electrically connected to a second thin film transistor; a second pixel electrode electrically connected with the second thin film transistor; a first touch sensing electrode corresponding to the first pixel electrode and insulated from the first pixel electrode; a second touch sensing electrode corresponding to the second pixel electrode and insulated from the second pixel electrode; a first sensing line electrically connected with the first touch sensing electrode; and a second sensing line electrically connected with the second touch sensing electrode, wherein the first data line overlaps with the first touch sensing electrode and the second touch sensing electrode, and the second data line overlaps with the first touch sensing electrode and the second touch sensing electrode.

Abstract: A semiconductor device includes a substrate including a first region, and a second region, a first gate structure and a second gate structure on the substrate of the first region, a third gate structure and a fourth gate structure on the substrate of the second region, a first interlayer insulating film on the substrate of the first region and including a first lower interlayer insulating film and a first upper interlayer insulating film, a second interlayer insulating film on the substrate of the second region and including a second lower interlayer insulating film and a second upper interlayer insulating film, a first contact between the first gate structure and the second gate structure and within the first interlayer insulating film, and a second contact formed between the third gate structure and the fourth gate structure and within the second interlayer insulating film.

Abstract: The present invention relates to a logical cell, a secondary battery module, and a secondary battery pack including the same, and particularly relates to a logical cell, in which a pouch cell assembly in which a plurality of pouch cells are arranged is accommodated inside a case in a longitudinal direction to form a logical cell, and a reinforcing plate is provided at one side or the other side of the case to reinforce rigidity, thereby facilitating handling of the pouch cell and maximizing space utilization, and simultaneously, preventing the side that is vulnerable to an impact from being damaged so that the secondary battery is improved in safety, a secondary battery module, and a secondary battery pack including the same.

Abstract: Disclosed is an LCD device which realizes decreased thickness, simplified process, and decreased cost by using a common electrode for formation of electric field to drive liquid crystal as a sensing electrode, and removing a touch screen from an upper surface of the liquid crystal panel, the LCD device comprising gate and data lines crossing each other to define plural pixels on a lower substrate; a pixel electrode in each of the plural pixels; plural common electrode blocks patterned at the different layer from the pixel electrode, wherein the common electrode blocks, together with the pixel electrode, forms an electric field, and senses a user's touch; and plural sensing lines electrically connected with the common electrode blocks, wherein, if the sensing line is electrically connected with one of the common electrode blocks, the sensing line is insulated from the remaining common electrode blocks.

Abstract: A semiconductor device includes a via pattern in a first interlayer insulating film, and a wiring pattern that extends in a first direction and is on the first interlayer insulating film and the via pattern. The wiring pattern includes a lower wiring line and an upper wiring line on the lower wiring line, where the lower wiring line and the upper wiring line are stacked in a second direction, where the lower wiring line is between the via pattern and the upper wiring line and is on an upper surface of the via pattern, where a first portion of the lower wiring line is on the upper surface of the via pattern and has a first thickness, and where a second portion of the lower wiring line is on an upper surface of the first interlayer insulating film and has a second thickness.

Abstract: A device including processors configured to execute instructions and memories storing the instructions, which when executed by the processors configure the processors to perform an operation for training a transformer model having a plurality of encoders and a plurality of decoders by configuring the processors to identify the batches of training data into a plurality of micro-batches, select layer pairs for the plurality of micro-batches, assemble a processing order of the layer pairs, determining resource information to be allocated to the layer pairs, and allocate resources to the layer pairs based on the determined resource information to be allocated to the layer pairs, dependent con the processing order of the layer pairs.

Abstract: A battery module includes a battery cell assembly formed by stacking two or more columns of longitudinal unit cells, each of which is composed of two or more battery cells arranged in a line in a longitudinal direction and connected, a hollow center guard disposed at a connection position of end portions of the battery cells, which face each other in the longitudinal direction, in the longitudinal unit cell, and a module case in which the battery cell assembly and the hollow center guard are accommodated, wherein a first venting hole communicating with a hollow of the hollow center guard is provided in a sidewall of the hollow center guard, and a second venting hole communicating with the hollow of the hollow center guard is provided in the module case configured to cover an upper portion of the hollow center guard. A battery pack includes the battery module.

Abstract: A device and method with batch normalization are provided. An accelerator includes: core modules, each core module including a respective plurality of cores configured to perform a first convolution operation using feature map data and a weight; local reduction operation modules adjacent to the respective core modules, each including a respective plurality of local reduction operators configured to perform a first local operation that obtains first local statistical values of the corresponding core module; a global reduction operation module configured to perform a first global operation that generates first global statistical values of the core module based on the first local statistical values of the core modules; and a normalization operation module configured to perform a first normalization operation on the feature map data based on the first global statistical values.

Abstract: A semiconductor device includes a substrate including a first region, and a second region, a first gate structure and a second gate structure on the substrate of the first region, a third gate structure and a fourth gate structure on the substrate of the second region, a first interlayer insulating film on the substrate of the first region and including a first lower interlayer insulating film and a first upper interlayer insulating film, a second interlayer insulating film on the substrate of the second region and including a second lower interlayer insulating film and a second upper interlayer insulating film, a first contact between the first gate structure and the second gate structure and within the first interlayer insulating film, and a second contact formed between the third gate structure and the fourth gate structure and within the second interlayer insulating film.

Abstract: A device including processors configured to execute instructions and memories storing the instructions, which when executed by the processors configure the processors to perform an operation for training a transformer model having a plurality of encoders and a plurality of decoders by configuring the processors to identify the batches of training data into a plurality of micro-batches, select layer pairs for the plurality of micro-batches, assemble a processing order of the layer pairs, determining resource information to be allocated to the layer pairs, and allocate resources to the layer pairs based on the determined resource information to be allocated to the layer pairs, dependent con the processing order of the layer pairs.

Abstract: A battery module includes a battery cell assembly formed by stacking two or more columns of longitudinal unit cells, each of which is composed of two or more battery cells arranged in a line in a longitudinal direction and connected, a hollow center guard disposed at a connection position of end portions of the battery cells, which face each other in the longitudinal direction, in the longitudinal unit cell, and a module case in which the battery cell assembly and the hollow center guard are accommodated, wherein a first venting hole communicating with a hollow of the hollow center guard is provided in a sidewall of the hollow center guard, and a second venting hole communicating with the hollow of the hollow center guard is provided in the module case configured to cover an upper portion of the hollow center guard. A battery pack includes the battery module.

Abstract: A semiconductor device includes a substrate including a first region, and a second region, a first gate structure and a second gate structure on the substrate of the first region, a third gate structure and a fourth gate structure on the substrate of the second region, a first interlayer insulating film on the substrate of the first region and including a first lower interlayer insulating film and a first upper interlayer insulating film, a second interlayer insulating film on the substrate of the second region and including a second lower interlayer insulating film and a second upper interlayer insulating film, a first contact between the first gate structure and the second gate structure and within the first interlayer insulating film, and a second contact formed between the third gate structure and the fourth gate structure and within the second interlayer insulating film.

Abstract: There is provided a semiconductor device capable of capable of improving element performance and reliability. A semiconductor device includes a lower conductive pattern disposed on a substrate, an upper conductive pattern disposed on the lower conductive pattern, and a first plug pattern disposed between the lower conductive pattern and the upper conductive pattern and connected to the lower conductive pattern and the upper conductive pattern. The first plug pattern includes a first barrier pattern that defines a first plug recess and a first plug metal pattern that fills the first plug recess, and the first plug metal pattern includes a first molybdenum pattern and a first tungsten pattern disposed on the first molybdenum pattern.

Abstract: An LCD device includes a plurality of gate lines and data lines cross-arranged on a lower substrate to define a plurality of pixels, a pixel electrode disposed in each of the pixels, a plurality of common electrode blocks pattern-formed that generate an electric field with the pixel electrode and sensing a touch of a user, a plurality of sensing lines, a plurality of pad parts arranged to be separated from each other at predetermined intervals along a corresponding sensing line, and having a line width thicker than the sensing line, and a contact part disposed between a corresponding pad part and a corresponding common electrode block, and electrically connecting a corresponding sensing line and the common electrode block. When the sensing lines are electrically connected to one of the common electrode blocks, the sensing lines are electrically insulated from the other common electrode blocks.