Abstract: A system for providing a compensated voltage used for precharging the detector/refreshing amplifiers in a charge-coupled memory employing a plurality of shift registers. A pair of dummy registers are used to generate a reference register output signal which is applied to a dummy sensor. The output of the dummy sensor is used to control, through a current source, the compensated voltage; the compensated voltage is used to pre-charge the dummy sensor. The system is particularly adaptable for an MOS CCD memory employing two layer polycrystalline silicon technology.

Abstract: A serial memory employing a plurality of charge-coupled shift registers fabricated with MOS technology and using double layer polycrystalline silicon gates. Each shift register includes two pairs of parallel channels; charge flows in opposite directions in each pair of channels. Multiplexing is utilized to refresh charge between each pair of channels through two refreshing amplifiers, one disposed at each end of the channels. The topographical efficiency of the design permits fabrication of a dense memory.