Abstract: Disclosed is an inverter which includes a first P-MOS transistor connected between a node receiving a drain voltage and a first path node and operated based on an input voltage, a first N-MOS transistor connected between the first path node and an output terminal outputting an output voltage and operated based on the drain voltage, a second P-MOS transistor connected between the output terminal and a second path node and operated based on a ground voltage, a second N-MOS transistor connected between the second path node and a node receiving the ground voltage and operated based on the input voltage, a third P-MOS transistor connected between the first path node and the second path node and operated based on the input voltage, and a third N-MOS transistor connected between the first path node and the second path node and operated based on the input voltage.

Abstract: A circuit includes a first full adder, a second full adder, a first half adder, a third full adder configured to receive a sum output signal of the first full adder, a sum output signal of the second full adder, and a sum output signal of the first half adder, a fourth full adder configured to receive a carry output signal of the first full adder, a carry output signal of the second full adder, and a carry output signal of the first half adder, a second half adder configured to receive a carry output signal of the third full adder and a sum output signal of the fourth full adder, and a third half adder configured to receive a carry output signal of the second half adder and a carry output signal of the fourth full adder.

Abstract: A static ternary gate is disclosed. The static ternary gate includes a drain-ground path configured to output a drain voltage through a first transistor when a first pull-up circuit is turned on, and output a ground voltage through a second transistor when a first pull-down circuit is turned on, a half-drain path configured to output a half-drain voltage through the first transistor and the second transistor when both a second pull-up circuit and a second pull-down circuit are turned on. The first transistor is configured to connect a node between the first pull-up circuit and the second pull-down circuit to an output terminal, and the second transistor is configured to connect a node between the second pull-up circuit and the first pull-down circuit to the output terminal.

Abstract: Disclosed is an inverter which includes a first P-MOS transistor connected between a node receiving a drain voltage and a first path node and operated based on an input voltage, a first N-MOS transistor connected between the first path node and an output terminal outputting an output voltage and operated based on the drain voltage, a second P-MOS transistor connected between the output terminal and a second path node and operated based on a ground voltage, a second N-MOS transistor connected between the second path node and a node receiving the ground voltage and operated based on the input voltage, a third P-MOS transistor connected between the first path node and the second path node and operated based on the input voltage, and a third N-MOS transistor connected between the first path node and the second path node and operated based on the input voltage.

Abstract: A circuit includes a plurality of first counting gates, a first ternary half adder (THA) and a second THA that are connected to the plurality of first counting gates, a third THA configured to receive a sum output signal of the first THA and a sum output signal of the second THA, a first ternary sum gate configured to receive a carry output signal of the first THA and a carry output signal of the second THA, and a second ternary sum gate configured to receive a carry output signal of the third THA and an output signal of the first ternary sum gate, wherein the third THA and the second ternary sum gate may be configured to output voltage signals corresponding to a number of drain voltages among input signals applied to the plurality of first counting gates.

Abstract: A circuit includes a first full adder, a second full adder, a first half adder, a third full adder configured to receive a sum output signal of the first full adder, a sum output signal of the second full adder, and a sum output signal of the first half adder, a fourth full adder configured to receive a carry output signal of the first full adder, a carry output signal of the second full adder, and a carry output signal of the first half adder, a second half adder configured to receive a carry output signal of the third full adder and a sum output signal of the fourth full adder, and a third half adder configured to receive a carry output signal of the second half adder and a carry output signal of the fourth full adder.

Abstract: A circuit includes a plurality of first counting gates, a first ternary half adder (THA) and a second THA that are connected to the plurality of first counting gates, a third THA configured to receive a sum output signal of the first THA and a sum output signal of the second THA, a first ternary sum gate configured to receive a carry output signal of the first THA and a carry output signal of the second THA, and a second ternary sum gate configured to receive a carry output signal of the third THA and an output signal of the first ternary sum gate, wherein the third THA and the second ternary sum gate may be configured to output voltage signals corresponding to a number of drain voltages among input signals applied to the plurality of first counting gates.

Abstract: A static ternary gate is disclosed. The static ternary gate includes a drain-ground path configured to output a drain voltage through a first transistor when a first pull-up circuit is turned on, and output a ground voltage through a second transistor when a first pull-down circuit is turned on, a half-drain path configured to output a half-drain voltage through the first transistor and the second transistor when both a second pull-up circuit and a second pull-down circuit are turned on. The first transistor is configured to connect a node between the first pull-up circuit and the second pull-down circuit to an output terminal, and the second transistor is configured to connect a node between the second pull-up circuit and the first pull-down circuit to the output terminal.

Abstract: Provided is a ternary logic synthesis method at least temporarily performed by a computer, the ternary logic synthesis method including generating a switching table with respect to pull-up and pull-down circuits using a truth table corresponding to a ternary function, converting the switching table into a sum of products (SOP) using a Quine-McCluskey algorithm, minimizing the SOP, and mapping a transistor corresponding to the SOP.

Abstract: Provided is a ternary logic synthesis method at least temporarily performed by a computer, the ternary logic synthesis method including generating a switching table with respect to pull-up and pull-down circuits using a truth table corresponding to a ternary function, converting the switching table into a sum of products (SOP) using a Quine-McCluskey algorithm, minimizing the SOP, and mapping a transistor corresponding to the SOP.