Abstract: Provided herein are compounds that promote targeted degradation of IKZF1, IKZF2, GSPT1, and/or CK1a, proteins whose activities are implicated in the pathology of certain cancers (e.g., acute myeloid leukemia). Also provided are pharmaceutical compositions comprising the compounds. Also provided are methods of treating cancer, and methods of promoting the degradation of IKZF1, IKZF2, GSPT1, and/or CK1a in a subject or biological sample by administering a compound or composition described herein.

Abstract: There are provided a semiconductor device and a manufacturing method of a semiconductor device. The semiconductor device includes: a gate structure including conductive layers and insulating layers, which are alternately stacked; channel structures penetrating the gate structure, the channel structures being arranged in a first direction; and a cutting structure extending in the first direction, the cutting structure consecutively penetrating the channel structures. Each of the channel structures includes a first channel structure and a second channel structure, which are isolated from each other by the cutting structure.

Abstract: A semiconductor memory device includes a lower stack in which a plurality of first interlayer insulating layers and first conductive layers are alternately stacked, a plurality of cell plugs penetrating the lower stack in a vertical direction, an upper stack in which a plurality of second interlayer insulating layers and at least one second conductive layer are alternately stacked on the lower stack, a plurality of drain select plugs penetrating the upper stack and overlapping the plurality of cell plugs, respectively, and a separation pattern penetrating the upper stack and disposed between at least two adjacent drain select plugs among the plurality of drain select plugs, wherein the at least two adjacent drain select plugs each have a semi-cylindrical shape and remaining drain select plugs except for the at least two adjacent drain select plugs among the plurality of drain select plugs each have a cylindrical shape.

Abstract: A semiconductor memory device, and a method of manufacturing the same, includes a lower stack in which a plurality of first interlayer insulating layers and first conductive layers are alternately stacked, a plurality of cell plugs passing through the lower stack in a vertical direction, an upper stack in which a plurality of second interlayer insulating layers and at least one second conductive layer are alternately stacked on the lower stack, a plurality of drain select plugs passing through the upper stack and being in contact with an upper portion of the plurality of cell plugs, and a separation pattern separating adjacent drain select plugs among the plurality of drain select plugs, wherein the separation pattern is in contact with a sidewall of each of the adjacent drain select plugs.

Abstract: A semiconductor memory device, and a method of manufacturing the same, includes a lower stack in which a plurality of first interlayer insulating layers and first conductive layers are alternately stacked, a plurality of cell plugs passing through the lower stack in a vertical direction, an upper stack in which a plurality of second interlayer insulating layers and at least one second conductive layer are alternately stacked on the lower stack, a plurality of drain select plugs passing through the upper stack and being in contact with an upper portion of the plurality of cell plugs, and a separation pattern separating adjacent drain select plugs among the plurality of drain select plugs, wherein the separation pattern is in contact with a sidewall of each of the adjacent drain select plugs.

Abstract: A semiconductor memory device, and a method of manufacturing the same, includes a lower stack in which a plurality of first interlayer insulating layers and first conductive layers are alternately stacked, a plurality of cell plugs passing through the lower stack in a vertical direction, an upper stack in which a plurality of second interlayer insulating layers and at least one second conductive layer are alternately stacked on the lower stack, a plurality of drain select plugs passing through the upper stack and being in contact with an upper portion of the plurality of cell plugs, and a separation pattern separating adjacent drain select plugs among the plurality of drain select plugs, wherein the separation pattern is in contact with a sidewall of each of the adjacent drain select plugs.

Abstract: The present invention relates to treatment of dry eye syndrome using a tanfanercept-containing ophthalmic composition. According to the present invention, as a result of clinical trial on dry eye syndrome, the tanfanercept-containing ophthalmic composition demonstrated excellent effects with regard to improvement of a central corneal staining score (CCSS) and a total corneal staining score (TCSS), which is clinically important. Further, such improvement of a central corneal staining score (CCSS) and a total corneal staining score (TCSS) was more significantly demonstrated in the patients with moderate-to-severe severity of dry eye. In addition, the patients with higher ocular discomfort score or higher eye dryness score, which are subjective symptoms, also showed greater improvement. Even though the same dose of tanfanercept was used, the tanfanercept-containing ophthalmic composition showed superior efficacy in the patient having more serious or severe baseline sign or symptom scores.

Abstract: Provided herein are compounds that promote targeted degradation of IKZF2, a protein whose activity is implicated in the pathology of certain cancers (e.g., acute myeloid leukemia). Also provided are pharmaceutical compositions comprising the compounds. Also provided are methods of treating cancer, and methods of promoting the degradation of IKZF2 in a subject or biological sample by administering a compound or composition described herein.

Abstract: There are provided a semiconductor device and a manufacturing method of a semiconductor device. The semiconductor device includes: a gate structure including conductive layers and insulating layers, which are alternately stacked; channel structures penetrating the gate structure, the channel structures being arranged in a first direction; and a cutting structure extending in the first direction, the cutting structure consecutively penetrating the channel structures. Each of the channel structures includes a first channel structure and a second channel structure, which are isolated from each other by the cutting structure.

Abstract: The present invention is directed to a method for producing induced electricity which prevents a collision by guiding induced electromagnetic force generated from a power generation coil as electricity is produced in the power generation coil to a predetermined location deviating from the path of power generation magnetic force which proceeds to be interlinked with the power generation coil to thus prevent power generation resistance from occurring and also produces electricity by interlinking the induced electromagnetic force with the power generation coil. The present invention is also directed to a “method for producing electricity using the induced electromagnetic force of a power generation coil” which uses an energy source for the production of electricity without conversion, so that there are no loss of energy during an energy conversion process and maintenance and management are easy, thereby reducing costs.

Abstract: A semiconductor memory device, and a method of manufacturing the same, includes a lower stack in which a plurality of first interlayer insulating layers and first conductive layers are alternately stacked, a plurality of cell plugs passing through the lower stack in a vertical direction, an upper stack in which a plurality of second interlayer insulating layers and at least one second conductive layer are alternately stacked on the lower stack, a plurality of drain select plugs passing through the upper stack and being in contact with an upper portion of the plurality of cell plugs, and a separation pattern separating adjacent drain select plugs among the plurality of drain select plugs, wherein the separation pattern is in contact with a sidewall of each of the adjacent drain select plugs.

Abstract: The present invention relates to an L-lysine-producing microorganism of the genus Corynebacterium and a method for producing L-lysine using the same.

Abstract: The present invention is directed to a method for producing induced electricity which prevents a collision by guiding induced electromagnetic force generated from a power generation coil as electricity is produced in the power generation coil to a predetermined location deviating from the path of power generation magnetic force which proceeds to be interlinked with the power generation coil to thus prevent power generation resistance from occurring and also produces electricity by interlinking the induced electromagnetic force with the power generation coil. The present invention is also directed to a “method for producing electricity using the induced electromagnetic force of a power generation coil” which uses an energy source for the production of electricity without conversion, so that there are no loss of energy during an energy conversion process and maintenance and management are easy, thereby reducing costs.

Abstract: The present invention relates to an L-lysine-producing microorganism of the genus Corynebacterium and a method for producing L-lysine using the same.

Abstract: A three dimensional (3-D) non-volatile memory device includes a pipe gate including a first pipe gate, a second pipe gate formed on the first pipe gate, and a first interlayer insulating layer interposed between the first pipe gate and the second pipe gate, word lines alternately stacked with second interlayer insulating layers on the pipe gate, a pipe channel buried within the pipe gate, and memory cell channels coupled to the pipe channel and arranged to pass through the word lines and the second interlayer insulating layers.

Abstract: The present invention relates to a large-area single-crystal monolayer graphene film in which a graphene layer is formed on a single-crystal metal catalyst layer whose crystal plane orientation is (111) optionally on a substrate. In the large-area single crystal monolayer graphene film of the present invention, a single-crystal metal catalyst layer whose crystal plane orientation is (111) can be formed in the shape of a foil, plate, block or tube optionally on a substrate and a graphene layer is formed on the catalyst layer. The present invention also relates to a method for producing a large-area single-crystal monolayer graphene film whose crystal plane orientation is (111) by annealing and chemical vapor deposition of a metal precursor.

Abstract: A three dimensional (3-D) non-volatile memory device includes a pipe gate including a first pipe gate, a second pipe gate formed on the first pipe gate, and a first interlayer insulating layer interposed between the first pipe gate and the second pipe gate, word lines alternately stacked with second interlayer insulating layers on the pipe gate, a pipe channel buried within the pipe gate, and memory cell channels coupled to the pipe channel and arranged to pass through the word lines and the second interlayer insulating layers.

Abstract: The present invention provides a polyamide resin composition comprising (A) about 100 parts by weight of polyamide resin; (B) about 0.1 to about 50 parts by weight of titanium dioxide; and (C) about 1 to about 20 parts by weight of modified polyolefin, wherein the (C) modified polyolefin is prepared by grafting a monomer that is partially miscible with the polyamide resin into the main chain of the polyolefin.

Abstract: A capacitor of a semiconductor device includes a capacitor structure configured to include electrode layers and dielectric layers alternately stacked, edge regions each stepwise patterned, and a central region disposed between the edge regions, sacrificial layers disposed within the respective electrode layers in the edge regions of the capacitor structure, and support plugs formed in the central region of the capacitor structure and configured to penetrate the electrode layers and the dielectric layers.

Abstract: A three dimensional (3-D) non-volatile memory device includes a pipe gate including a first pipe gate, a second pipe gate formed on the first pipe gate, and a first interlayer insulating layer interposed between the first pipe gate and the second pipe gate, word lines alternately stacked with second interlayer insulating layers on the pipe gate, a pipe channel buried within the pipe gate, and memory cell channels coupled to the pipe channel and arranged to pass through the word lines and the second interlayer insulating layers.