Patents by Inventor Sunny Arora
Sunny Arora has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9723465Abstract: A system, station and corresponding methods for providing warning notifications. In one exemplary method, it is determined whether any of a plurality of stations to which a Warning Notification is to transmitted is in a connected state. When it is determined that a first one of the stations is in a connected state, generating, by a broadcaster, a secondary Warning Notification formatted for transmission over a dedicated control channel (DCCH) and transmitting, by the broadcaster, the secondary Warning Notification to the first station over the DCCH. In another exemplary embodiment, a station for receiving emergency notifications is described. The station includes a receiver configured to receive a primary Warning Notification; and a processor which, upon receiving the emergency alert configuration in a format of one of a Paging Type 2 message and an SICI message, despreads a plurality of fingers.Type: GrantFiled: September 30, 2014Date of Patent: August 1, 2017Assignee: APPLE INC.Inventors: Umesh Shukla, Sunny Arora, Mohan Rao Thota
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Patent number: 9398545Abstract: A method, station and computer readable storage medium used for setting a power level of the station. The station implements a first processing layer that is a radio link control layer and a second processing layer that is a physical layer. The method includes receiving data units of a voice application, the data units being in a sequence, determining whether the first processing layer of the station detects a gap in the sequence of received data units, communicating an indication from the first processing layer to the second processing layer, the indication indicating at least one identity of corresponding missing data units in the gap relative to the first processing layer and increasing the current power level when the at least one identity of the corresponding missing data units relative to the first processing layer is also determined to be a missing data unit relative to the second processing layer.Type: GrantFiled: May 30, 2014Date of Patent: July 19, 2016Assignee: APPLE INC.Inventors: Sai Sravan Bharadwaj Karri, Sunny Arora, Arjun Bhupathi Raju
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Patent number: 9271223Abstract: A method for adaptive filtering of cell measurements is provided. The method can include a wireless communication device determining based on instantaneous measurement samples of a cell captured over a measurement period that a fading condition of the cell exceeds a threshold. The method can further include the wireless communication device modifying a network configured filter coefficient to derive a modified filter coefficient in response to the fading condition of the cell exceeding the threshold over the measurement period. The method can additionally include the wireless communication device filtering the instantaneous measurement samples based on the modified filter coefficient to calculate a filtered measurement of the cell. The method can also include the wireless communication device calculating an adjusted measurement value for the cell based on the filtered measurement.Type: GrantFiled: March 1, 2013Date of Patent: February 23, 2016Assignee: Apple Inc.Inventors: Sai Sravan Bharadwaj Karri, Sunny Arora
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Publication number: 20150351049Abstract: A method, station and computer readable storage medium used for setting a power level of the station. The station implements a first processing layer that is a radio link control layer and a second processing layer that is a physical layer. The method includes receiving data units of a voice application, the data units being in a sequence, determining whether the first processing layer of the station detects a gap in the sequence of received data units, communicating an indication from the first processing layer to the second processing layer, the indication indicating at least one identity of corresponding missing data units in the gap relative to the first processing layer and increasing the current power level when the at least one identity of the corresponding missing data units relative to the first processing layer is also determined to be a missing data unit relative to the second processing layer.Type: ApplicationFiled: May 30, 2014Publication date: December 3, 2015Applicant: APPLE INC.Inventors: Sai Sravan Bharadwaj KARRI, Sunny ARORA, Arjun Bhupathi RAJU
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Publication number: 20150195696Abstract: A system, station and corresponding methods for providing warning notifications. In one exemplary method, it is determined whether any of a plurality of stations to which a Warning Notification is to transmitted is in a connected state. When it is determined that a first one of the stations is in a connected state, generating, by a broadcaster, a secondary Warning Notification formatted for transmission over a dedicated control channel (DCCH) and transmitting, by the broadcaster, the secondary Warning Notification to the first station over the DCCH. In another exemplary embodiment, a station for receiving emergency notifications is described. The station includes a receiver configured to receive a primary Warning Notification; and a processor which, upon receiving the emergency alert configuration in a format of one of a Paging Type 2 message and an SICI message, despreads a plurality of fingers.Type: ApplicationFiled: September 30, 2014Publication date: July 9, 2015Inventors: Umesh SHUKLA, Sunny ARORA, Mohan Rao THOTA
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Patent number: 8965444Abstract: A particular method includes transmitting a message corresponding to a reporting event detected at a mobile device, where the reporting event is associated with a network condition that decreases a likelihood of the mobile device successfully decoding a reply to the message. The method also includes, in response to transmitting the message, increasing a signal-to-interference ratio (SIR) target of the mobile device.Type: GrantFiled: January 10, 2012Date of Patent: February 24, 2015Assignee: Qualcomm IncorporatedInventors: Harish Venkatachari, An-swol C. Hu, Rajiv R. Nambiar, Venkata Chalapathi Rao S. Emani, Ravi Gopalan, Sunny Arora
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Publication number: 20140248840Abstract: A method for adaptive filtering of cell measurements is provided. The method can include a wireless communication device determining based on instantaneous measurement samples of a cell captured over a measurement period that a fading condition of the cell exceeds a threshold. The method can further include the wireless communication device modifying a network configured filter coefficient to derive a modified filter coefficient in response to the fading condition of the cell exceeding the threshold over the measurement period. The method can additionally include the wireless communication device filtering the instantaneous measurement samples based on the modified filter coefficient to calculate a filtered measurement of the cell. The method can also include the wireless communication device calculating an adjusted measurement value for the cell based on the filtered measurement.Type: ApplicationFiled: March 1, 2013Publication date: September 4, 2014Applicant: APPLE INC.Inventors: Sai Sravan Bharadwaj Karri, Sunny Arora
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Patent number: 8464117Abstract: A system for scan testing various clock domains of an integrated circuit includes a clock gate control unit and clock gating cells. The clock gating cells receive a single test clock signal provided externally through one package pin of the integrated circuit. The clock gate control unit provides clock gate control signals to the clock gating cells. The clock gating cells generate time-staggered clock signals based on the clock gate control signals.Type: GrantFiled: May 25, 2010Date of Patent: June 11, 2013Assignee: Freescale Semiconductor, Inc.Inventors: Shruti Rakheja, Sunny Arora, Pawan Deep Gandhi, Rashmi Moudgil
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Publication number: 20130012254Abstract: A particular method includes transmitting a message corresponding to a reporting event detected at a mobile device, where the reporting event is associated with a network condition that decreases a likelihood of the mobile device successfully decoding a reply to the message. The method also includes, in response to transmitting the message, increasing a signal-to-interference ratio (SIR) target of the mobile device.Type: ApplicationFiled: January 10, 2012Publication date: January 10, 2013Inventors: Harish Venkatachari, An-swol C. Hu, Rajiv R. Nambiar, Venkata Chalapathi Rao S. Emani, Ravi Gopalan, Sunny Arora
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Patent number: 8120404Abstract: A flip-flop circuit with an internal level shifter includes an input stage, a clock input stage, an output stage and a level shifting stage. The output stage generates an output signal based on an input signal received by the input stage and a clock signal received by the clock input stage. The level shifting stage shifts-up the voltage level of the output signal.Type: GrantFiled: April 29, 2011Date of Patent: February 21, 2012Assignee: Freescale Semiconductor, Inc.Inventors: Sunny Arora, Kumar Abhishek, Mukesh Bansal, Shilpa Gupta
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Publication number: 20110296265Abstract: A system for scan testing various clock domains of an integrated circuit includes a clock gate control unit and clock gating cells. The clock gating cells receive a single test clock signal provided externally through one package pin of the integrated circuit. The clock gate control unit provides clock gate control signals to the clock gating cells. The clock gating cells generate time-staggered clock signals based on the clock gate control signals.Type: ApplicationFiled: May 25, 2010Publication date: December 1, 2011Applicant: FREESCALE SEMICONDUCTOR, INCInventors: Shruti RAKHEJA, Sunny Arora, Pawan Deep Gandhi, Rashmi Moudgil
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Publication number: 20110199139Abstract: A flip-flop circuit with an internal level shifter includes an input stage, a clock input stage, an output stage and a level shifting stage. The output stage generates an output signal based on an input signal received by the input stage and a clock signal received by the clock input stage. The level shifting stage shifts-up the voltage level of the output signal.Type: ApplicationFiled: April 29, 2011Publication date: August 18, 2011Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Sunny ARORA, Kumar Abhishek, Mukesh Bansal, Shilpa Gupta
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Patent number: 7956662Abstract: A flip-flop circuit with an internal level shifter includes an input stage, a clock input stage, an output stage and a level shifting stage. The output stage generates an output signal based on an input signal received by the input stage and a clock signal received by the clock input stage. The level shifting stage shifts-up the voltage level of the output signal.Type: GrantFiled: November 23, 2009Date of Patent: June 7, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Sunny Arora, Kumar Abhishek, Mukesh Bansal, Shilpa Gupta
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Patent number: 7834657Abstract: An inverter circuit has a digital signal amplitude converter having an input coupled to an inverter circuit input node, and an amplitude converter output. A positive threshold voltage compensation generator has a positive threshold voltage compensation generator input coupled to the amplitude converter output. A negative threshold voltage compensation generator has a negative threshold voltage compensation generator input coupled to the inverter circuit input node, and a negative threshold voltage compensation generator output. A multiplexer has a first input coupled to the positive threshold voltage compensation generator output, a second input, coupled to the negative threshold voltage compensation generator output, and a multiplexer output. An inverter module has an output providing an inverter circuit output node, and an inverter module input is coupled to the multiplexer output.Type: GrantFiled: January 12, 2010Date of Patent: November 16, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Sunny Arora, Mukesh Bansal, Dipesh K. Gupta, Ankesh Jain, Gaurav Jain, Ritika Singh
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Publication number: 20100182063Abstract: A flip-flop circuit with an internal level shifter includes an input stage, a clock input stage, an output stage and a level shifting stage. The output stage generates an output signal based on an input signal received by the input stage and a clock signal received by the clock input stage. The level shifting stage shifts-up the voltage level of the output signal.Type: ApplicationFiled: November 23, 2009Publication date: July 22, 2010Applicant: Freescale Semiconductor, Inc.Inventors: Sunny ARORA, Kumar Abhishek, Mukesh Bansal, Shilpa Gupta