Abstract: A mode-controlled voltage excursion detector apparatus for monitoring a supply voltage of a power supply applied to a load and a method of operating thereof is described. A voltage monitor is configured to detect an excursion event if the supply voltage exceeds or falls below at least one defined threshold, to generate an excursion event signal upon detection of the excursion event and to provide the generated excursion event signal to the excursion event output for being outputted via an excursion event output. A sensitivity control module is configured to receive a signal indicative of potential voltage excursions. A sensitivity control module is further operatively coupled to the sensitivity control input and configured to disable the outputting of an excursion event signal generated during a defined period of time in response to the reception of the signal, which triggers the disabling of the outputting.

Abstract: In an embodiment, an electronic device includes an integrated circuit (IC) having a plurality of power domains, a first regulator coupled to a given power domain, a second regulator coupled to the given power domain, and a switching circuit coupled between the first and second regulators and configured to control an amount of current drawn by the power domain from the first and/or second regulators. In another embodiment, a method includes controlling an impedance of a switching circuit to change an amount of current, the switching circuit coupled to a given power domain of an IC configured to operate in a first mode followed by a second mode, where the switching circuit is coupled to a first regulator configured to provide more power to the IC than a second regulator, and a transition period includes turning off the first regulator and turning on the second regulator.

Abstract: An integrated circuit (IC) operable in functional and debug modes includes a debug enable circuit, a pad control register, a debug circuit, a pad configuration register, and an input/output (IO) pad. The debug circuit receives a functional signal from a circuit monitoring circuit, a reference signal, a debug control signal from the debug enable circuit, and pull-enable control and pull-type select control signals from the pad control register, and generates pull-enable and pull-type select signals. The pad configuration register receives the pull-enable and pull-type select signals and configures the IO pad in one of logic low, logic high, and high impedance states. When the IO pad is in either of the logic high and low states longer than a predetermined time period, then the IO pad indicates that the IC is held in a reset phase of a reset sequence.

Abstract: An integrated circuit and a method of self-testing the integrated circuit are provided. The method comprises: generating a reference voltage at an output of a reference circuit; initiating a test of the reference circuit during a test mode; determining whether the test of the reference circuit passes; and comparing, if the test of the reference circuit passes, a first voltage with the reference voltage. The disclosed test method provides for more complete testing of the integrated circuit.

Abstract: Methods and systems for evaluating the electrical activity of the heart to identify novel ECG patterns closely linked to the subsequent development of serious heart rhythm disturbances and fatal cardiac events. Two approaches are describe, for example a model-based analysis and space-time analysis, which are used to study the dynamical and geometrical properties of the ECG data. In the first a model is derived using a modified Matching Pursuit (MMP) algorithm. Various metrics and subspaces are extracted to characterize the risk for serious heart rhythm disturbances, sudden cardiac death, other modes of death, and all-cause mortality linked to different electrical abnormalities of the heart. In the second method, space-time domain is divided into a number of regions (e.g., 12 regions), the density of the ECG signal is computed in each region and input to a learning algorithm to associate them with these events.

Abstract: An integrated circuit (IC) includes a digital-to-analog converter (DAC), a voltage monitoring circuit, and a controller. The voltage monitoring circuit includes low voltage detect (LVD) and low voltage warning (LVW) circuits that generate LVD and LVW reference voltage signals. The controller generates and stores a voltage margin word (a difference between first and second DAC words that correspond to the LVD and LVW reference voltage signals, respectively). The controller compares the voltage margin word with predetermined maximum and minimum voltage margin words. If the voltage margin word does not lie between the predetermined maximum and minimum voltage margin words, the controller generates a voltage trimming signal that scales the LVW reference voltage signal. After scaling, if the voltage margin word lies between the predetermined maximum and minimum voltage margin words, the controller generates a calibration pass signal, otherwise the controller generates a calibration fail signal.

Abstract: The present disclosure uses physiological data, ECG signals as an example, to evaluate cardiac structure and function in mammals. Two approaches are presented, e.g., a model-based analysis and a space-time analysis. The first method uses a modified Matching Pursuit (MMP) algorithm to find a noiseless model of the ECG data that is sparse and does not assume periodicity of the signal. After the model is derived, various metrics and subspaces are extracted to image and characterize cardiovascular tissues using complex-sub-harmonic-frequencies (CSF) quasi-periodic and other mathematical methods. In the second method, space-time domain is divided into a number of regions, the density of the ECG signal is computed in each region and inputted into a learning algorithm to image and characterize the tissues.

Abstract: An integrated circuit (IC) includes a reference voltage generator, a voltage regulator, a reset controller, and a voltage monitoring circuit. The reference voltage generator generates first and second reference voltages, and the voltage regulator generates a supply voltage. The reset controller stabilizes the first and second reference voltages in a first predetermined time period, and generates a power down signal after the first predetermined time period. The voltage monitoring circuit compares a level of the supply voltage with a level of the second reference voltage after the first predetermined time period and generates a (low) voltage monitor signal. The reset controller also generates a (high) reset signal when the supply voltage is greater than the second reference voltage.

Abstract: An integrated circuit (IC) operable in functional and debug modes includes a debug enable circuit, a pad control register, a debug circuit, a pad configuration register, and an input/output (IO) pad. The debug circuit receives a functional signal from a circuit monitoring circuit, a reference signal, a debug control signal from the debug enable circuit, and pull-enable control and pull-type select control signals from the pad control register, and generates pull-enable and pull-type select signals. The pad configuration register receives the pull-enable and pull-type select signals and configures the IO pad in one of logic low, logic high, and high impedance states. When the IO pad is in either of the logic high and low states longer than a predetermined time period, then the IO pad indicates that the IC is held in a reset phase of a reset sequence.

Abstract: An integrated circuit (IC) includes a digital-to-analog converter (DAC), a voltage monitoring circuit, and a controller. The voltage monitoring circuit includes low voltage detect (LVD) and low voltage warning (LVW) circuits that generate LVD and LVW reference voltage signals. The controller generates and stores a voltage margin word (a difference between first and second DAC words that correspond to the LVD and LVW reference voltage signals, respectively). The controller compares the voltage margin word with predetermined maximum and minimum voltage margin words. If the voltage margin word does not lie between the predetermined maximum and minimum voltage margin words, the controller generates a voltage trimming signal that scales the LVW reference voltage signal. After scaling, if the voltage margin word lies between the predetermined maximum and minimum voltage margin words, the controller generates a calibration pass signal, otherwise the controller generates a calibration fail signal.

Abstract: A reset state control circuit adapted to reset independent device domains of an electronic device, said reset state control circuit comprising a capturing unit adapted to capture reset events; and a reset shaping logic adapted to change dynamically a reset control flow to reset device domains of said electronic device depending on a sequence of the reset events captured by said capturing unit.

Abstract: The present disclosure uses physiological data, ECG signals as an example, to evaluate cardiac structure and function in mammals. Two approaches are presented, e.g., a model-based analysis and a space-time analysis. The first method uses a modified Matching Pursuit (MMP) algorithm to find a noiseless model of the ECG data that is sparse and does not assume periodicity of the signal. After the model is derived, various metrics and subspaces are extracted to image and characterize cardiovascular tissues using complex-sub-harmonic-frequencies (CSF) quasi-periodic and other mathematical methods. In the second method, space-time domain is divided into a number of regions, the density of the ECG signal is computed in each region and inputted into a learning algorithm to image and characterize the tissues.

Abstract: The present application relates to a mode-controlled voltage excursion detector apparatus for monitoring a supply voltage of a power supply applied to a load and a method of operating thereof. A voltage monitor is configured to detect an excursion event if the supply voltage exceeds or falls below at least one defined threshold, to generate an excursion event signal upon detection of the excursion event and to provide the generated excursion event signal to the excursion event output for being outputted via an excursion event output. A sensitivity control module is configured to receive a signal indicative of potential voltage excursions. A sensitivity control module is further operatively coupled to the sensitivity control input and configured to disable the outputting of an excursion event signal generated during a defined period of time in response to the reception of the signal, which triggers the disabling of the outputting.

Abstract: An integrated circuit (IC) that operates in high and low power modes includes high and low power regulators, first and second sets of circuits, a switch connecting the high power regulator and the second set of circuits, and a wake-up control system. The wake-up control system includes a state machine that enables the high power regulator when the IC is in the high power mode, and enables the low power regulator when the IC is in the low power mode. The switch is closed when the high power regulator reaches a first threshold voltage. The state machine operates on a low frequency clock signal when the IC is in the low power mode and during wake-up, and on a high frequency clock signal in the high power mode after the switch is closed.

Abstract: A power management system for an integrated circuit (IC) includes low and full-power bandgap generators, first and second multiplexers, first circuitry, and a full-power regulator. When the IC is powered on, the first multiplexer selects the full-power bandgap generator as a reference voltage source for the first circuitry. After the low-power bandgap generator has been trimmed, the first multiplexer selects the low-power bandgap generator as the reference voltage source for the first circuitry. When the IC transitions from low power mode to high power mode, the second multiplexer selects the low-power bandgap generator as the reference voltage source for the full-power regulator. When the full-power bandgap generator is powered on, the second multiplexer selects the full-power bandgap generator as the reference voltage source for the full-power regulator.

Abstract: An integrated circuit (IC) with voltage regulation includes high power and low power domains, low and high voltage regulators and a low power regulator. The low voltage regulator powers the high and low power domains when the IC is in a HIGH power mode. The low power regulator receives a voltage from a high voltage regulator and powers the low power domain when the IC is in a LOW power mode. The IC includes a switching module that disconnects the low voltage regulator from the low power domain when the output voltage of the high voltage regulator is lower than a threshold voltage during power-up and connects the low voltage regulator to the low power domain when the voltage regulated by the high voltage regulator exceeds the threshold voltage.

Abstract: Methods to identify and risk stratify disease states, cardiac structural defects, functional cardiac deficiencies induced by teratogens and other toxic agents, pathological substrates, conduction delays and defects, and ejection fraction using single channel biological data obtained from the subject. A modified Matching Pursuit (MP) algorithm may be used to find a noiseless model of the data that is sparse and does not assume periodicity of the signal. After the model is derived, various metrics and subspaces are extracted to characterize the cardiac system. In another method, space-time domain is divided into a number of regions (which is largely determined by the signal length), the density of the signal is computed in each region and input to a learning algorithm to associate them to the desired cardiac dysfunction indicator target.

Abstract: Systems and methods for managing cold-crank events. In an embodiment, a method may include detecting a cold-crank event and setting a switching circuit to a non-conductive state, where the switching circuit is configured to couple a first regulator to a memory circuit such that setting the switching circuit to the non-conductive state de-couples the memory circuit from the first regulator. The method may also include setting the switching circuit to a conductive state in current limitation mode during a recovery period following the cold-crank event to re-couple the memory circuit to the first regulator. In another embodiment, an electronic device include a switching circuit, a first regulator coupled to a first terminal of the switching circuit, a second regulator coupled to a second terminal of the switching circuit, a logic circuit coupled to the switching circuit, and a memory circuit coupled to the second terminal of the switching circuit.

Abstract: An integrated circuit (IC) with voltage regulation includes high power and low power domains, low and high voltage regulators and a low power regulator. The low voltage regulator powers the high and low power domains when the IC is in a HIGH power mode. The low power regulator receives a voltage from a high voltage regulator and powers the low power domain when the IC is in a LOW power mode. The IC includes a switching module that disconnects the low voltage regulator from the low power domain when the output voltage of the high voltage regulator is lower than a threshold voltage during power-up and connects the low voltage regulator to the low power domain when the voltage regulated by the high voltage regulator exceeds the threshold voltage.

Abstract: In an embodiment, an electronic device includes an integrated circuit (IC) having a plurality of power domains, a first regulator coupled to a given power domain, a second regulator coupled to the given power domain, and a switching circuit coupled between the first and second regulators and configured to control an amount of current drawn by the power domain from the first and/or second regulators. In another embodiment, a method includes controlling an impedance of a switching circuit to change an amount of current, the switching circuit coupled to a given power domain of an IC configured to operate in a first mode followed by a second mode, where the switching circuit is coupled to a first regulator configured to provide more power to the IC than a second regulator, and a transition period includes turning off the first regulator and turning on the second regulator.