Abstract: Systems and methods are provided for testing a Device Under Test (DUT) in its working environment. A control computer is coupled to an air compressor and generates a temperature control signal that is provided to the air compressor to generate an amount of hot air or cold air to set the temperature of the DUT's working environment to a desired test temperature. The control computer also generates at least one test signal that is sent to a hardware test element for testing at least one memory component of the DUT at the desired test temperature and obtaining test results. The control computer analyzes the test results to determine a parameter adjustment for the at least one memory element so that it operates in a stable manner at the test temperature.

Abstract: Systems and methods are provided for testing a Device Under Test (DUT) in its working environment. A control computer is coupled to an air compressor and generates a temperature control signal that is provided to the air compressor to generate an amount of hot air or cold air to set the temperature of the DUT's working environment to a desired test temperature. The control computer also generates at least one test signal that is sent to a hardware test element for testing at least one memory component of the DUT at the desired test temperature and obtaining test results. The control computer analyzes the test results to determine a parameter adjustment for the at least one memory element so that it operates in a stable manner at the test temperature.

Abstract: Various embodiments are described herein for a testing system for performing burn-in testing of electronic devices under a test temperature range using at least one test chamber and a tester. The at least one test chamber is doorless and has a frame defining a chamber opening for receiving at least one burn-in board containing the electronic devices. The tester includes a main frame, a plurality of carrier magazines mounted to the main frame and containing the at least one burn-in board containing the electronic devices, a door panel at a front end of the tester to allow for access into the tester; and a wall panel disposed on a surface opposite the door panel. The wall panel is placed adjacent and secured to the chamber opening of the at least one test chamber to provide an air and temperature seal during testing.

Abstract: Various embodiments are described herein for a testing system for performing burn-in testing of electronic devices under a test temperature range using at least one test chamber and a tester. The at least one test chamber is doorless and has a frame defining a chamber opening for receiving at least one burn-in board containing the electronic devices. The tester includes a main frame, a plurality of carrier magazines mounted to the main frame and containing the at least one burn-in board containing the electronic devices, a door panel at a front end of the tester to allow for access into the tester; and a wall panel disposed on a surface opposite the door panel. The wall panel is placed adjacent and secured to the chamber opening of the at least one test chamber to provide an air and temperature seal during testing.

Abstract: Various embodiments are described herein for testing memory devices more effectively and taking corrective action or for identifying memory devices. For example, a particular set of memory cells may be used for testing and/or for identifying a memory device. In other cases, memory testing may be done with a particular subset of test patterns.

Abstract: Embodiments described herein relate to systems and methods for testing and assembling memory modules. In at least one embodiment, the method comprises: assembling a memory module, the memory module comprising at least one memory device having one or more defective memory locations; wherein the assembling comprises storing the data that identifies the one or more defective memory locations on the memory device in a persistent store on the memory module, wherein the memory module comprises a microprocessor and persistent memory associated with the microprocessor, and wherein the persistent store on the memory module comprises the persistent memory associated with the microprocessor.

Abstract: Various embodiments are described herein for a system and a method for increasing reliability of a secondary storage device used with a computing system where the secondary storage device contains a memory buffer, a controller, and non-volatile memory. The method may comprise initializing a test of the memory buffer; testing at least one memory block of the memory buffer; discontinuing use of a given memory block of the memory buffer if a defective memory location is detected for the given memory block; and storing test results for the memory buffer.

Abstract: Embodiments of systems and methods for testing memory are disclosed, where memory errors are detected, and, in at least one embodiment, memory units containing errors are prevented from being accessed by applications on a computing system.

Abstract: Systems and methods are provided to determine a solid operating timing window for an integrated circuit device, and the solid operating timing window used to determine a key timing index. A method for determining the solid operating timing window is disclosed. A plurality of sets of operating parameters is generated. For each of the plurality of sets of operating parameters, the respective set of operating parameters is applied to a test environment. The integrated circuit is then operated under the applied respective set of operating parameters. A determining a data valid window is determined for the integrated circuit. The solid operating timing window for the integrated circuit is then determined using the data valid windows for the plurality of sets of operating parameters, where the solid operating timing window is defined as the logical intersection of the determined data valid windows such that the integrated circuit will return valid sample.

Abstract: Embodiments of a system and method for testing an integrated circuit device are described herein. Testing is complemented by a determination of characteristics of a data valid window that identifies components of a response data signal from a device under test where the data signal can always be expected to be stable.

Abstract: Embodiments described herein relate to systems and methods for testing and assembling memory modules. In at least one embodiment, the method comprises: assembling a memory module, the memory module comprising at least one memory device having one or more defective memory locations; wherein the assembling comprises storing the data that identifies the one or more defective memory locations on the memory device in a persistent store on the memory module, wherein the memory module comprises a microprocessor and persistent memory associated with the microprocessor, and wherein the persistent store on the memory module comprises the persistent memory associated with the microprocessor.

Abstract: Embodiments of systems and methods for testing memory are disclosed, where memory errors are detected, and, in at least one embodiment, memory units containing errors are prevented from being accessed by applications on a computing system.

Abstract: Systems and methods are provided to determine a solid operating timing window for an integrated circuit device, the solid timing window used to determine a key timing index. The key timing index provides an indication of the quality of an integrated circuit over a range of operating conditions. In at least one embodiment a method is provided, the method comprising generating a plurality of combinations of operating parameters, for each of the plurality of combinations of operating parameters setting the respective combination of operating parameters, operating the integrated circuit under the set respective combination of operating parameters, and determining a data valid window for the integrated circuit. The solid operating timing window for the integrated circuit is then determined using the data valid windows for the plurality of combinations of operating parameters, where the solid operating timing window is the logical intersection of the determined data valid windows.

Abstract: A testing apparatus for analyzing a memory module under test operating within an application system, wherein the memory module under test is coupled to a processor of the application system, is disclosed herein. In at least one embodiment, the testing apparatus comprises a first interface for coupling to the application system, a second interface for coupling to a reference memory module, a controller coupled to the first and second interfaces, at least one comparator, and a data logging unit. The data logging unit is configured to receive logging data from the controller and at least one test result from the at least one comparator, and to record, in a memory, at least a subset of the logging data, such that more specific details of memory errors revealed during behavioral testing of memory modules may be identified, examined, and stored for subsequent analysis.

Abstract: Embodiments of a system and method for testing an integrated circuit device are described herein. Testing is complemented by a determination of characteristics of a data valid window that identifies components of a response data signal from a device under test where the data signal can always be expected to be stable.

Abstract: A testing apparatus for analyzing a memory module under test operating within an application system, wherein the memory module under test is coupled to a processor of the application system, is disclosed herein. In at least one embodiment, the testing apparatus comprises a first interface for coupling to the application system, a second interface for coupling to a reference memory module, a controller coupled to the first and second interfaces, at least one comparator, and a data logging unit. The data logging unit is configured to receive logging data from the controller and at least one test result from the at least one comparator, and to record, in a memory, at least a subset of the logging data, such that more specific details of memory errors revealed during behavioral testing of memory modules may be identified, examined, and stored for subsequent analysis.

Abstract: Embodiments described herein relate to systems and methods for testing integrated circuit devices within an environment that is representative of the application environment in which an integrated circuit device will be used. In at least one embodiment, the testing system comprises a second reference integrated circuit device that provides flexibility in testing, allowing only the input to a first reference integrated circuit device of an application system to be tapped and not necessarily both input to and output from the first reference integrated circuit device to be tapped. In some embodiments, the input to the first reference integrated circuit device may be subsequently modified by a controller.

Abstract: A system and method for testing an integrated circuit module including multiple integrated circuit devices that provide a data strobe signal associated with at least one data signal provided by the same integrated circuit device. A determination of a test outcome for the integrated circuit module may be made after identifying data valid windows for each integrated circuit device, without having to both identify a common sampling window defined by an intersection of the identified data valid windows and verify that such common sampling window meets specification requirements.

Abstract: Embodiments described herein relate to systems and methods for testing integrated circuit devices within an environment that is representative of the application environment in which an integrated circuit device will be used.

Abstract: Embodiments of an apparatus and method for high-speed testing of a device under test are described herein, where the device under test is coupled to a tester via a limited passband communication channel. A plurality of test vector patterns is generated having characteristics such that when a given test vector pattern is transmitted electrically at a transmission rate via the communication channel, the test vector pattern has a frequency content that is less than the frequency content of a high frequency test vector pattern if the high frequency test vector pattern were to be transmitted electrically at the transmission rate via the communication channel, and such that the frequency content of each test vector pattern when transmitted electrically at the transmission rate via the communication channel falls within the passband associated with the communication channel.