Patents by Inventor SunYoung Chun

SunYoung Chun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8932908
    Abstract: A semiconductor device has a substrate with a die attach area. A conductive layer is formed over a surface of the substrate and extending below the surface. An insulating layer is formed over the surface of the substrate outside the die attach area. A portion of the conductive layer is removed within the die attach area to expose sidewalls of the substrate. The remaining portion of the conductive layer is recessed below the surface of the substrate within the die attach area. A semiconductor die has bumps formed over its active surface. The semiconductor die is mounted to the substrate by bonding the bumps to the remaining portion of the first conductive layer recessed below the first surface of the substrate. The sidewalls of the substrate retain the bumps during bonding to the remaining portion of the conductive layer. An encapsulant is deposited between the semiconductor die and substrate.
    Type: Grant
    Filed: May 17, 2013
    Date of Patent: January 13, 2015
    Assignee: STATS ChipPAC, Ltd.
    Inventors: KyuWon Lee, HyunSu Shin, Hun Jeong, JinGwan Kim, SunYoung Chun
  • Publication number: 20130249090
    Abstract: A semiconductor device has a substrate with a die attach area. A conductive layer is formed over a surface of the substrate and extending below the surface. An insulating layer is formed over the surface of the substrate outside the die attach area. A portion of the conductive layer is removed within the die attach area to expose sidewalls of the substrate. The remaining portion of the conductive layer is recessed below the surface of the substrate within the die attach area. A semiconductor die has bumps formed over its active surface. The semiconductor die is mounted to the substrate by bonding the bumps to the remaining portion of the first conductive layer recessed below the first surface of the substrate. The sidewalls of the substrate retain the bumps during bonding to the remaining portion of the conductive layer. An encapsulant is deposited between the semiconductor die and substrate.
    Type: Application
    Filed: May 17, 2013
    Publication date: September 26, 2013
    Applicant: STATS ChipPAC, Ltd.
    Inventors: KyuWon Lee, HyunSu Shin, Hun Jeong, JinGwan Kim, SunYoung Chun
  • Patent number: 8502392
    Abstract: A semiconductor device has a substrate with a die attach area. A conductive layer is formed over a surface of the substrate and extending below the surface. An insulating layer is formed over the surface of the substrate outside the die attach area. A portion of the conductive layer is removed within the die attach area to expose sidewalls of the substrate. The remaining portion of the conductive layer is recessed below the surface of the substrate within the die attach area. A semiconductor die has bumps formed over its active surface. The semiconductor die is mounted to the substrate by bonding the bumps to the remaining portion of the first conductive layer recessed below the first surface of the substrate. The sidewalls of the substrate retain the bumps during bonding to the remaining portion of the conductive layer. An encapsulant is deposited between the semiconductor die and substrate.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: August 6, 2013
    Assignee: STATS ChipPAC, Ltd.
    Inventors: KyuWon Lee, HyunSu Shin, Hun Jeong, JinGwan Kim, SunYoung Chun
  • Patent number: 8432028
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a base substrate having a base substrate top side; mounting a base integrated circuit over the base substrate top side, the base integrated circuit having an active side opposite an inactive side with the inactive side facing the base substrate top side; attaching a peripheral interconnect to the base substrate top side and a device peripheral pad of the base integrated circuit at the active side; mounting an interposer over the base integrated circuit and the peripheral interconnect, the interposer having an interposer top side and a window; and attaching a central interconnect to the interposer top side and a device central pad of the base integrated circuit at the active side, the central interconnect through the window.
    Type: Grant
    Filed: March 21, 2011
    Date of Patent: April 30, 2013
    Assignee: STATS ChipPAC Ltd.
    Inventors: JinGwan Kim, KyuWon Lee, MoonKi Jeong, SunYoung Chun, JiHoon Oh
  • Publication number: 20120326303
    Abstract: A semiconductor device has a substrate with a die attach area. A conductive layer is formed over a surface of the substrate and extending below the surface. An insulating layer is formed over the surface of the substrate outside the die attach area. A portion of the conductive layer is removed within the die attach area to expose sidewalls of the substrate. The remaining portion of the conductive layer is recessed below the surface of the substrate within the die attach area. A semiconductor die has bumps formed over its active surface. The semiconductor die is mounted to the substrate by bonding the bumps to the remaining portion of the first conductive layer recessed below the first surface of the substrate. The sidewalls of the substrate retain the bumps during bonding to the remaining portion of the conductive layer. An encapsulant is deposited between the semiconductor die and substrate.
    Type: Application
    Filed: September 7, 2012
    Publication date: December 27, 2012
    Applicant: STATS CHIPPAC, LTD.
    Inventors: KyuWon Lee, HyunSu Shin, Hun Jeong, JinGwan Kim, SunYoung Chun
  • Patent number: 8288202
    Abstract: A semiconductor device has a substrate with a die attach area. A conductive layer is formed over a surface of the substrate and extending below the surface. An insulating layer is formed over the surface of the substrate outside the die attach area. A portion of the conductive layer is removed within the die attach area to expose sidewalls of the substrate. The remaining portion of the conductive layer is recessed below the surface of the substrate within the die attach area. A semiconductor die has bumps formed over its active surface. The semiconductor die is mounted to the substrate by bonding the bumps to the remaining portion of the first conductive layer recessed below the first surface of the substrate. The sidewalls of the substrate retain the bumps during bonding to the remaining portion of the conductive layer. An encapsulant is deposited between the semiconductor die and substrate.
    Type: Grant
    Filed: November 22, 2010
    Date of Patent: October 16, 2012
    Assignee: STATS ChiPAC, Ltd.
    Inventors: KyuWon Lee, HyunSu Shin, Hun Jeong, JinGwan Kim, SunYoung Chun
  • Publication number: 20120241936
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a base substrate having a base substrate top side; mounting a base integrated circuit over the base substrate top side, the base integrated circuit having an active side opposite an inactive side with the inactive side facing the base substrate top side; attaching a peripheral interconnect to the base substrate top side and a device peripheral pad of the base integrated circuit at the active side; mounting an interposer over the base integrated circuit and the peripheral interconnect, the interposer having an interposer top side and a window; and attaching a central interconnect to the interposer top side and a device central pad of the base integrated circuit at the active side, the central interconnect through the window.
    Type: Application
    Filed: March 21, 2011
    Publication date: September 27, 2012
    Inventors: JinGwan Kim, KyuWon Lee, MoonKi Jeong, SunYoung Chun, JiHoon Oh
  • Publication number: 20120126416
    Abstract: A semiconductor device has a substrate with a die attach area. A conductive layer is formed over a surface of the substrate and extending below the surface. An insulating layer is formed over the surface of the substrate outside the die attach area. A portion of the conductive layer is removed within the die attach area to expose sidewalls of the substrate. The remaining portion of the conductive layer is recessed below the surface of the substrate within the die attach area. A semiconductor die has bumps formed over its active surface. The semiconductor die is mounted to the substrate by bonding the bumps to the remaining portion of the first conductive layer recessed below the first surface of the substrate. The sidewalls of the substrate retain the bumps during bonding to the remaining portion of the conductive layer. An encapsulant is deposited between the semiconductor die and substrate.
    Type: Application
    Filed: November 22, 2010
    Publication date: May 24, 2012
    Applicant: STATS CHIPPAC, LTD.
    Inventors: KyuWon Lee, HyunSu Shin, Hun Jeong, JinGwan Kim, SunYoung Chun
  • Patent number: 8004093
    Abstract: An integrated circuit package stacking system includes: forming a flexible substrate by: providing an insulating material, forming a stacking pad on the insulating material, forming a coupling pad on the insulating material, and forming a trace between the stacking pad and the coupling pad; providing a package substrate; coupling an integrated circuit to the package substrate; and applying a conductive adhesive on the package substrate for positioning the flexible substrate over the integrated circuit and coupling the flexible substrate on the conductive adhesive.
    Type: Grant
    Filed: August 1, 2008
    Date of Patent: August 23, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: JiHoon Oh, JinGwan Kim, Jaehyun Lim, SunYoung Chun, KyuWon Lee, SinJae Lee, JongVin Park
  • Publication number: 20100025835
    Abstract: An integrated circuit package stacking system includes: forming a flexible substrate by: providing an insulating material, forming a stacking pad on the insulating material, forming a coupling pad on the insulating material, and forming a trace between the stacking pad and the coupling pad; providing a package substrate; coupling an integrated circuit to the package substrate; and applying a conductive adhesive on the package substrate for positioning the flexible substrate over the integrated circuit and coupling the flexible substrate on the conductive adhesive.
    Type: Application
    Filed: August 1, 2008
    Publication date: February 4, 2010
    Inventors: JiHoon Oh, JinGwan Kim, Jaehyun Lim, SunYoung Chun, KyuWon Lee, SinJae Lee, JongVin Park