Patents by Inventor Suparna Behera

Suparna Behera has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7698477
    Abstract: A method and apparatus is provided wherein a central Credit Controller Entity (CCE) is connected to a PCIE fabric environment by means of several buses. Flow Control information sent to the CCE over two of the buses indicates the buffer storage capacity that is available at respective Receiver components in the PCIE fabric. The CCE processes the Flow Control information, to generate updates that are sent by a third bus to Transmitter components corresponding to the Receivers. In one useful embodiment, directed to a method of Flow Control management, the CCE provides a repository adapted to store credit count information that represents the available storage capacity of respective Receivers. The method further comprises routing further credit count information from a given Receiver to the CCE, for storage in the repository, following each of successive events that affect the storage capacity of the given Receiver.
    Type: Grant
    Filed: November 30, 2005
    Date of Patent: April 13, 2010
    Assignee: LSI Corporation
    Inventors: Jeffrey William Breti, Douglas Elliott Sanders, Harish Bharadwaj, Suparna Behera, Gordon Douglas Boyd, Richard John Bombard, Philip Waldron Herman, Jr.
  • Patent number: 7571370
    Abstract: A method and circuit for performing CRC calculations permits variable width data input. Preferably, multiple CRC calculations are performed in parallel, each CRC calculation involving a different number of data bits from the data word and terminating within one clock cycle. The CRC polynomial is preferably incorporated into the hardware for each CRC calculation.
    Type: Grant
    Filed: June 19, 2003
    Date of Patent: August 4, 2009
    Assignee: LSI Logic Corporation
    Inventors: Jeremy Ridgeway, Suparna Behera, Ravindra Viswanath
  • Publication number: 20070121495
    Abstract: A method and apparatus is provided wherein a central Credit Controller Entity (CCE) is connected to a PCIE fabric environment by means of several buses. Flow Control information sent to the CCE over two of the buses indicates the buffer storage capacity that is available at respective Receiver components in the PCIE fabric. The CCE processes the Flow Control information, to generate updates that are sent by a third bus to Transmitter components corresponding to the Receivers. In one useful embodiment, directed to a method of Flow Control management, the CCE provides a repository adapted to store credit count information that represents the available storage capacity of respective Receivers. The method further comprises routing further credit count information from a given Receiver to the CCE, for storage in the repository, following each of successive events that affect the storage capacity of the given Receiver.
    Type: Application
    Filed: November 30, 2005
    Publication date: May 31, 2007
    Inventors: Jeffrey Breti, Douglas Sanders, Harish Bharadwaj, Suparna Behera, Gordon Boyd, Richard Bombard, Philip Herman
  • Publication number: 20050005224
    Abstract: A method and circuit for performing CRC calculations permits variable width data input. Preferably, multiple CRC calculations are performed in parallel, each CRC calculation involving a different number of data bits from the data word and terminating within one clock cycle. The CRC polynomial is preferably incorporated into the hardware for each CRC calculation.
    Type: Application
    Filed: June 19, 2003
    Publication date: January 6, 2005
    Inventors: Jeremy Ridgeway, Suparna Behera, Ravindra Viswanath