Abstract: Disclosed is a computer-implemented method for degassing for the manufacture of a high speed design. The method includes analyzing information related to a printed circuit board (PCB) that includes a set of layers and a plurality of voids. The method identifies a void from the plurality of voids, where the void has a position among the PCB set of layers. The method determines a radius associated with the identified void, where the radius is based on a center of the identified void. The method performs a trace selection and executes a shift algorithm based on the trace selection, where the shift algorithm includes a modification of the information related to the void. As a result, the method can generate a grid for degassing based on execution of the shift algorithm. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: The disclosed computer-implemented method for automatically generating a printed circuit board design includes executing, by at least one processor based on input parameters, a grouping operation that identifies network shapes defining regions occupied by corresponding networks for one or more layers of an integrated circuit package. The method additionally includes identifying, by the at least one processor based on the identified network shapes, connections of the integrated circuit package. The method also includes automatically generating, by the at least one processor and based on the identified connections, a printed circuit board design. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: Disclosed is a computer-implemented method for degassing for the manufacture of a high speed design. The method includes analyzing information related to a printed circuit board (PCB) that includes a set of layers and a plurality of voids. The method identifies a void from the plurality of voids, where the void has a position among the PCB set of layers. The method determines a radius associated with the identified void, where the radius is based on a center of the identified void. The method performs a trace selection and executes a shift algorithm based on the trace selection, where the shift algorithm includes a modification of the information related to the void. As a result, the method can generate a grid for degassing based on execution of the shift algorithm. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: A package that includes a substrate having a first surface; a solder resist layer coupled to the first surface of the substrate; a device located over the solder resist layer such that a portion of the device touches the solder resist layer; and an encapsulation layer located over the solder resist layer such that the encapsulation layer encapsulates the device. The solder resist layer is configured as a seating plane for the device. The device is located over the solder resist layer such that a surface of the device facing the substrate is approximately parallel to the first surface of the substrate. The solder resist layer includes at least one notch. The device is located over the solder resist layer such that at least one corner of the device touches the at least one notch.

Abstract: An integrated circuit (IC) package is described. The IC package includes a laminate substrate. The IC package also includes an active die on a surface of the laminate substrate. The IC package further includes fin-based thermal surface mount devices on the surface of the laminate substrate proximate the active die to provide an additional heat dissipation path.

Abstract: An integrated circuit (IC) package is described. The IC package includes a laminate substrate. The IC package also includes an active die on a surface of the laminate substrate. The IC package further includes fin-based thermal surface mount devices on the surface of the laminate substrate proximate the active die to provide an additional heat dissipation path.

Abstract: A package that includes a substrate having a first surface; a solder resist layer coupled to the first surface of the substrate; a device located over the solder resist layer such that a portion of the device touches the solder resist layer; and an encapsulation layer located over the solder resist layer such that the encapsulation layer encapsulates the device. The solder resist layer is configured as a seating plane for the device. The device is located over the solder resist layer such that a surface of the device facing the substrate is approximately parallel to the first surface of the substrate. The solder resist layer includes at least one notch. The device is located over the solder resist layer such that at least one corner of the device touches the at least one notch.