Abstract: The present disclosure relates to the field of communication technologies, and provide a near-field communication (NFC) chip, a phase synchronization method, and an electronic device, to quickly synchronize a transmitted signal of an NFC card device with a carrier of an NFC card reader. The NFC chip includes a processing circuit configured to: determine a first carrier frequency offset between a local clock signal and a carrier clock signal, and generate a first frequency control word based on the first carrier frequency offset. The carrier clock signal is determined based on a received signal received by the NFC chip. The NFC chip further includes a phase-locked loop configured to generate a first clock signal based on the local clock signal and the first frequency control word.

Abstract: A time-to-digital converter (TDC) is disclosed, which comprises a ring oscillator module and a digital error correction module. The ring oscillator module is configured to receive a sampling signal, an addressing signal, and a preset signal, and includes: a ring oscillator arranged with a plurality of inverters; a phase sampler configured to sample phase signals generated by the inverters for generating a first output signal; a counter clock generator configured to generate first and second clock signals; first and second counters configured to respectively generate first and second counter output signals; and a data sampler configured to sample the first and second counter output signals to respectively generate second and third output signals. The digital error correction module is arranged to process the first, second and third output signals for generating a digital signal.

Abstract: A time-to-digital converter (TDC) is disclosed, which comprises a ring oscillator module and a digital error correction module. The ring oscillator module is configured to receive a sampling signal, an addressing signal, and a preset signal, and includes: a ring oscillator arranged with a plurality of inverters; a phase sampler configured to sample phase signals generated by the inverters for generating a first output signal; a counter clock generator configured to generate first and second clock signals; first and second counters configured to respectively generate first and second counter output signals; and a data sampler configured to sample the first and second counter output signals to respectively generate second and third output signals. The digital error correction module is arranged to process the first, second and third output signals for generating a digital signal.