Abstract: An apparatus and method for efficiently routing power signals across a semiconductor die. In various implementations, an integrated circuit includes a micro through silicon via (TSV) that traverses a silicon substrate layer to a backside metal layer. The integrated circuit also includes power switches. The integrated circuit routes a power supply signal from the output of a power switch to a frontside power rail using the micro TSV and the backside metal layer. The integrated circuit also routes the power supply signal from the output of the power switch to the frontside power rail using a frontside metal layer. Therefore, the frontside metal layer and the backside metal layer provide power connection redundancy that increases charge sharing, improves wafer yield, reduces voltage droop, and reduces on-die area. In addition, the process routes a ground reference voltage level using both a frontside power rail and a backside power rail.