Abstract: In a single wire communications interface embodiment, a single wire is coupled between a master device and at least one slave device, the master device configured for transmitting data words as serial data to and for receiving data words as serial data from the at least one slave device, and the at least one slave device configured for transmitting data words as serial data to and receiving data words as serial data from the master device; wherein prior to transmission of any data word on the single wire by one of the master device and the slave device, a sync pulse is first transmitted on the single wire. Integrated circuit embodiments for implementing the single wire communications interface, and method embodiments incorporating the single wire communications interface are disclosed. Additional embodiments are disclosed.

Abstract: The disclosure provides a current steering digital to analog converter (DAC) that includes a plurality of DAC elements. At least one DAC element of the plurality of DAC elements is coupled to a calibration circuit. The calibration circuit includes a fixed current source coupled to a primary node of the DAC element through a first estimation switch. A digital code generator is coupled to the primary node, and generates a first digital code corresponding to a primary voltage generated at the primary node. The digital code generator generates a second digital code. A correction DAC is coupled to the digital code generator and generates a bias voltage based on the second digital code. The bias voltage is provided to the DAC element such that a current flowing through each DAC element of the plurality of DAC elements is equal.

Abstract: The disclosure provides a current steering digital to analog converter (DAC) that includes a plurality of DAC elements. At least one DAC element of the plurality of DAC elements is coupled to a calibration circuit. The calibration circuit includes a fixed current source coupled to a primary node of the DAC element through a first estimation switch. A digital code generator is coupled to the primary node, and generates a first digital code corresponding to a primary voltage generated at the primary node. The digital code generator generates a second digital code. A correction DAC is coupled to the digital code generator and generates a bias voltage based on the second digital code. The bias voltage is provided to the DAC element such that a current flowing through each DAC element of the plurality of DAC elements is equal.

Abstract: In a single wire communications interface embodiment, a single wire is coupled between a master device and at least one slave device, the master device configured for transmitting data words as serial data to and for receiving data words as serial data from the at least one slave device, and the at least one slave device configured for transmitting data words as serial data to and receiving data words as serial data from the master device; wherein prior to transmission of any data word on the single wire by one of the master device and the slave device, a sync pulse is first transmitted on the single wire. Integrated circuit embodiments for implementing the single wire communications interface, and method embodiments incorporating the single wire communications interface are disclosed. Additional embodiments are disclosed.

Abstract: An offset correction circuit examines a residue signal of a stage of a pipeline analog to digital converter (ADC) to determine whether a parameter which could cause offset error, needs to be adjusted. In an embodiment, the parameter is adjusted until a maximum range of the residue signal equals an expected range. In the described examples, the adjusted parameters include timing offset error (when components of an ADC sample the input signal at different time instances) and a voltage offset error (the threshold voltage at which a sub-ADC in a stage the generated sub-code changes to a next value).

Abstract: An offset correction circuit examines a residue signal of a stage of a pipeline analog to digital converter (ADC) to determine whether a parameter which could cause offset error, needs to be adjusted. In an embodiment, the parameter is adjusted until a maximum range of the residue signal equals an expected range. In the described examples, the adjusted parameters include timing offset error (when components of an ADC sample the input signal at different time instances) and a voltage offset error (the threshold voltage at which a sub-ADC in a stage the generated sub-code changes to a next value).