Abstract: The present disclosure relates to a computer-implemented method for electronic design is provided. Embodiments may include receiving, using at least one processor, an electronic design having one or more unoptimized nets. Embodiments may further include applying a genetic algorithm to the electronic design, wherein the genetic algorithm includes a multi-stage routing analysis. A first stage analysis may apply a device-level global routing analysis, a second stage analysis may include an intra-row routing analysis, a third stage may include an inter-row routing analysis, and a fourth stage may include a post-routing optimization analysis. Embodiments may also include generating an optimized routing of the one or more unoptimized nets and displaying the optimized routing at a graphical user interface.

Abstract: Various embodiments implement high current carrying multi-strands of interconnects between two pins in a region of interest within an electronic circuit by performing area-based searches for viable routing solutions using valid intervals. Certain pins that are within a predetermined proximity to each other may be optionally clustered to form a single, wide pin. The region of interest may be first processed to form one or more sets of spacetiles, or the geometries in the region of interest may be projected onto a boundary of the region of interest, to determine the valid interval(s) on along the boundary. The valid intervals may then be used by a router to implement the multi-strands of interconnects. The router also considers the physical, electrical, and manufacturing requirement(s) in implementing the multi-strands of interconnects.

Abstract: Various embodiments identify a design including circuit features and identify an operation that produces an aggressor for victim(s). The operation on the aggressor and the set of victims are implemented using local maximally spanning spacetile(s) while satisfying some design requirements. Where the set of victims includes interconnects, the design may allow no bend in some interconnects. One or more spacetiles are used to perform the operation on the aggressor and implement the interconnects while introducing no bends in the interconnects by using local maximally spanning spacetile(s). Some implementation may perform block modeling for the aggressor to perform the operation on the aggressor and implement a set of victims while preserving the relative order of the interconnects by using the block modeling for the aggressor.

Abstract: Various embodiments identify a design including circuit features and identify an operation that produces an aggressor for victim(s). The operation on the aggressor and the set of victims are implemented using local maximally spanning spacetile(s) while satisfying some design requirements. Where the set of victims includes interconnects, the design may allow no bend in some interconnects. One or more spacetiles are used to perform the operation on the aggressor and implement the interconnects while introducing no bends in the interconnects by using local maximally spanning spacetile(s). Some implementation may perform block modeling for the aggressor to perform the operation on the aggressor and implement a set of victims while preserving the relative order of the interconnects by using the block modeling for the aggressor.