Patents by Inventor Surachai Sutha

Surachai Sutha has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7742620
    Abstract: A method for identifying potential targets as far away as possible is disclosed. In a simple background scene such as a blue sky, a target may be recognized from a relatively long distance, but for some high clutter situations such as mountains and cities, the detection range is severely reduced. The background clutter may also be non-stationary further complicating the detection of a target. To solve these problems, target detection (recognition) of the present invention is based upon temporal fusion (integration) of sensor data using pre-detection or post-detection integration techniques, instead of using the prior art technique of fusing data from only a single time frame. Also disclosed are double-thresholding and reversed-thresholding techniques which further enhance target detection and avoid the shortcomings of the traditional constant false alarm rate (CFAR) thresholding technique.
    Type: Grant
    Filed: March 18, 2004
    Date of Patent: June 22, 2010
    Assignee: Lockhead Martin Corporation
    Inventors: Hai-Wen Chen, Teresa L. Olson, Surachai Sutha
  • Publication number: 20070076917
    Abstract: A method for identifying potential targets as far away as possible is disclosed. In a simple background scene such as a blue sky, a target may be recognized from a relatively long distance, but for some high clutter situations such as mountains and cities, the detection range is severely reduced. The background clutter may also be non-stationary further complicating the detection of a target. To solve these problems, target detection (recognition) of the present invention is based upon temporal fusion (integration) of sensor data using pre-detection or post-detection integration techniques, instead of using the prior art technique of fusing data from only a single time frame. Also disclosed are double-thresholding and reversed-thresholding techniques which further enhance target detection and avoid the shortcomings of the traditional constant false alarm rate (CFAR) thresholding technique.
    Type: Application
    Filed: March 18, 2004
    Publication date: April 5, 2007
    Applicant: LOCKHEED MARTIN CORPORATION
    Inventors: Hai-Wen Chen, Teresa Olson, Surachai Sutha
  • Patent number: 6298162
    Abstract: A fast method with logarithmic complexity for image compression and expansion is provided, implementable on the Geometric Arithmetic Parallel Processor (GAPP) or any similar fine-grained, mesh-connected Single Instruction-Multiple Datastream (SIMD) array processor. Efficient decomposition of the original image into multiple subimages enables the method to exploit the parallelism of the SIMD computer for implementing powerful multiresolution pyramid and hierarchical image processing techniques on a massively parallel processor.
    Type: Grant
    Filed: February 21, 1995
    Date of Patent: October 2, 2001
    Assignee: Lockheed Martin Corporation
    Inventors: Surachai Sutha, Dan T. Long
  • Patent number: 6185667
    Abstract: An apparatus for processing data has a Single-Instruction-Multiple-Data (SIMD) architecture, and a number of features that improve performance and programmability. The apparatus includes a rectangular array of processing elements and a controller. The apparatus offers a number of techniques for shifting image data within the array. A first technique, the ROLL option, simultaneously shifts image planes in opposite directions within the array. A second technique, the gated shift option, makes a normal shift of an image plane to neighboring PEs conditional, for each PE, upon a value stored in a pattern register of each PE. A third technique, the carry propagate option, combines the computations from multiple PEs in order to complete an n-bit operation in fewer than n clocks by forming “supercells” within the array. The apparatus also includes a multi-bit X Pattern register and a multi-bit Y Pattern register.
    Type: Grant
    Filed: April 9, 1998
    Date of Patent: February 6, 2001
    Assignee: TeraNex, Inc.
    Inventors: Andrew P. Abercrombie, Surachai Sutha, Wlodzimierz Holsztynski