Patents by Inventor Suraj Varma

Suraj Varma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230099916
    Abstract: Methods, systems, apparatuses, and computer program products are described. A system, such as a multi-tenant database system, may store tenant-specific observability data for multiple tenants of the system. The system may detect an inefficiency related to a performance metric for a tenant of the multiple tenants based on a subset of the data associated with the tenant and corresponding to a threshold time window. In some examples, the system may analyze the subset of the data for the threshold time window to determine an insight indicating a cause of the inefficiency. The system may determine a suggested action for the tenant based on the insight indicating the cause of the inefficiency, and the system may send, for display at a user interface of a user device, an indication of the insight and the suggested action, the user device operated by a user associated with the tenant.
    Type: Application
    Filed: September 23, 2022
    Publication date: March 30, 2023
    Inventors: Paymon Teyer, Alok K. Patel, Arjun Kumar Bachuwar, Suraj Varma, Jackson Zee Herrick, Karishma Kishore Lalwani
  • Patent number: 9158357
    Abstract: In at least one embodiment described herein, an apparatus is provided that can include means for communicating a latency tolerance value for a device connected to a platform from a software latency register if a software latency tolerance register mode is active. The apparatus may also include means for communicating the latency tolerance value from a hardware latency register if a host controller is active. The latency tolerance value can be sent to a power management controller. More specific examples can include means for communicating a latency tolerance value from the software latency register if the software latency tolerance register mode is not active and the host controller is not active. The apparatus can also include means for mapping a resource space in the software latency register for the device using a BIOS/platform driver. The mapping can be achieved using an advanced configuration and power interface device description.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: October 13, 2015
    Assignee: Intel Corporation
    Inventors: Jaya L. Jeyaseelan, Linda Weyhing, Rajeev Nalawadi, Barnes Cooper, Suraj Varma, Nevo Idan, David Poisner
  • Publication number: 20140189391
    Abstract: In at least one embodiment described herein, an apparatus is provided that can include means for communicating a latency tolerance value for a device connected to a platform from a software latency register if a software latency tolerance register mode is active. The apparatus may also include means for communicating the latency tolerance value from a hardware latency register if a host controller is active. The latency tolerance value can be sent to a power management controller. More specific examples can include means for communicating a latency tolerance value from the software latency register if the software latency tolerance register mode is not active and the host controller is not active. The apparatus can also include means for mapping a resource space in the software latency register for the device using a BIOS/platform driver. The mapping can be achieved using an advanced configuration and power interface device description.
    Type: Application
    Filed: December 28, 2012
    Publication date: July 3, 2014
    Inventors: Jaya L. Jeyaseelan, Linda Weyhing, Rajeev Nalawadi, Barnes Cooper, Suraj Varma, Nevo Idan, David Poisner