Patents by Inventor Surani Bin Dolmanan
Surani Bin Dolmanan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10763348Abstract: The invention provides a product and a manufacturing process for a high power semiconductor device. The semiconductor device comprises a GaN/AlGaN epilayer structure on an SOI substrate with a thick, uninterrupted GaN layer for use in high-power applications.Type: GrantFiled: December 3, 2019Date of Patent: September 1, 2020Assignee: Agency for Science, Technology and ResearchInventors: Krishna Kumar Manippady, Surani Bin Dolmanan, Kaixin Vivian Lin, Hui Ru Tan, Sudhiranjan Tripathy
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Patent number: 10679860Abstract: A method for fabrication of high electron mobility transistor (HEMT) semiconductor devices is presented. The method includes providing a substrate, growing a HEMT layer structure on the substrate; and self-aligned common metal stack formation of source, drain and gate electrodes on the HEMT layer structure using a single lithographic mask.Type: GrantFiled: March 9, 2016Date of Patent: June 9, 2020Assignee: AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCHInventors: Lakshmi Kanta Bera, Yee Chong Loke, Surani Bin Dolmanan, Sudhiranjan Tripathy, Wai Hoe Tham
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Publication number: 20200105915Abstract: The invention provides a product and a manufacturing process for a high power semiconductor device. The semiconductor device comprises a GaN/AlGaN epilayer structure on an SOI substrate with a thick, uninterrupted GaN layer for use in high-power applications.Type: ApplicationFiled: December 3, 2019Publication date: April 2, 2020Applicant: Agency for Science, Technology and ResearchInventors: Krishna Kumar Manippady, Surani Bin Dolmanan, Kaixin Vivian Lin, Hui Ru Tan, Sudhiranjan Tripathy
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Patent number: 10546949Abstract: Contemplated is a semiconductor device comprising: a substrate; a group (III)-nitride layer; a metal-group (III)-nitride layer deposited between the substrate and group (III)-nitride layer; and a metal-nitride layer deposited between the substrate and the metal-group (III)-nitride layer. Also a method for making a semiconductor device with the above mentioned structure is contemplated. Furthermore, the substrate can be a silicon on insulator (SOI) substrate; the metal-nitride layer can be an aluminium nitride layer; the metal-group (III)-nitride layer can be an aluminium gallium nitride layer; and the group (III)-nitride layer can be a gallium nitride layer.Type: GrantFiled: December 23, 2013Date of Patent: January 28, 2020Assignee: Agency for Science, Technology and ResearchInventors: Krishna Kumar Manippady, Surani Bin Dolmanan, Kaixin Vivian Lin, Hui Ru Tan, Sudhiranjan Tripathy
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Patent number: 9972709Abstract: There is provided a method for fabricating a semiconductor device having the following structure, and comprising the steps of growing a first and a second nucleation layer on a substrate; depositing a binary layer over these nucleation layers; and annealing the binary layer to form a first contact area and a second contact area on the substrate, wherein the annealed binary layer comprises a group 14 element selected from Si, Ge and their combination thereof, and the annealed binary layer in the first and second contact areas are capable of providing a lower contact resistance for a current to flow in the device. This method serves to provide an intermediate layer which enables the fabrication process to become CMOS compatible.Type: GrantFiled: April 4, 2017Date of Patent: May 15, 2018Assignee: AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCHInventors: Lakshmi Kanta Bera, Surani Bin Dolmanan, Manippady Krishna Kumar, Rasanayagam Sivasayan Kajen, Sudhiranjan Tripathy
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Patent number: 9954088Abstract: There is provided a method for fabricating a semiconductor device having the following structure, and comprising the steps of growing a nucleation layer on a substrate; depositing a binary layer over the nucleation layer; and annealing the binary layer to form a first contact area and a second contact area on the substrate, wherein the annealed binary layer comprises a group 14 element selected from Si, Ge or their combination thereof, and the annealed binary layer in the first and second contact areas are capable of providing a lower contact resistance for a current to flow in the device. This method serves to provide an intermediate layer which enables the fabrication process to become CMOS compatible.Type: GrantFiled: October 20, 2014Date of Patent: April 24, 2018Assignee: AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCHInventors: Lakshmi Kanta Bera, Surani Bin Dolmanan, Manippady Krishna Kumar, Rasanayagam Sivasayan Kajen, Sudhiranjan Tripathy
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Publication number: 20180033631Abstract: A method for fabrication of high electron mobility transistor (HEMT) semiconductor devices is presented. The method includes providing a substrate, growing a HEMT layer structure on the substrate; and self-aligned common metal stack formation of source, drain and gate electrodes on the HEMT layer structure using a single lithographic mask.Type: ApplicationFiled: March 9, 2016Publication date: February 1, 2018Applicant: Agency for Science, Technology and ResearchInventors: Lakshmi Kanta Bera, Yee Chong Loke, Surani Bin Dolmanan, Sudhiranjan Tripathy, Wai Hoe Tham
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Publication number: 20170222030Abstract: There is provided a method for fabricating a semiconductor device having the following structure, and comprising the steps of growing a first and a second nucleation layer on a substrate; depositing a binary layer over these nucleation layers; and annealing the binary layer to form a first contact area and a second contact area on the substrate, wherein the annealed binary layer comprises a group 14 element selected from Si, Ge and their combination thereof, and the annealed binary layer in the first and second contact areas are capable of providing a lower contact resistance for a current to flow in the device. This method serves to provide an intermediate layer which enables the fabrication process to become CMOS compatible.Type: ApplicationFiled: April 4, 2017Publication date: August 3, 2017Inventors: Lakshmi Kanta Bera, Surani Bin Dolmanan, Manippady Krishna Kumar, Rasanayagam Sivasayan Kajen, Sudhiranjan Tripathy
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Patent number: 9647183Abstract: There is provided a method of fabricating a vertical light emitting diode which includes forming a light emitting diode structure. Forming the light emitting diode structure includes: forming a first material layer of a first conductivity type, forming a second material layer of a second conductivity type, forming a light emitting layer between the first material layer and the second material layer, and forming a plurality of generally ordered photonic nanostructures at a surface of the first material layer through which light generated from the light emitting layer is emitted for enhancing light extraction efficiency of the vertical light emitting diode. In particular, forming a plurality of generally ordered photonic nanostructures includes forming a self-assembled template including generally ordered nanoparticles on the surface of the first material layer to function as a mask for forming the photonic nanostructures at said surface of the first material layer.Type: GrantFiled: October 30, 2015Date of Patent: May 9, 2017Assignee: Agency for Science, Technology and ResearchInventors: Sivashankar Krishnamoorthy, Krishna Kumar Manippady, Surani Bin Dolmanan, Kaixin Vivian Lin, Siew Lang Teo, Sudhiranjan Tripathy
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Publication number: 20160233325Abstract: There is provided a method for fabricating a semiconductor device having the following structure, and comprising the steps of growing a nucleation layer on a substrate; depositing a binary layer over the nucleation layer; and annealing the binary layer to form a first contact area and a second contact area on the substrate, wherein the annealed binary layer comprises a group 14 element selected from Si, Ge or their combination thereof, and the annealed binary layer in the first and second contact areas are capable of providing a lower contact resistance for a current to flow in the device. This method serves to provide an intermediate layer which enables the fabrication process to become CMOS compatible.Type: ApplicationFiled: October 20, 2014Publication date: August 11, 2016Inventors: Lakshmi Kanta BERA, Surani Bin DOLMANAN, Manippady Krishna KUMAR, Rasanayagam Sivasayan KAJEN, Sudhiranjan TRIPATHY
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Publication number: 20160049563Abstract: There is provided a method of fabricating a vertical light emitting diode which includes forming a light emitting diode structure. Forming the light emitting diode structure includes: forming a first material layer of a first conductivity type, forming a second material layer of a second conductivity type, forming a light emitting layer between the first material layer and the second material layer, and forming a plurality of generally ordered photonic nanostructures at a surface of the first material layer through which light generated from the light emitting layer is emitted for enhancing light extraction efficiency of the vertical light emitting diode. In particular, forming a plurality of generally ordered photonic nanostructures includes forming a self-assembled template including generally ordered nanoparticles on the surface of the first material layer to function as a mask for forming the photonic nanostructures at said surface of the first material layer.Type: ApplicationFiled: October 30, 2015Publication date: February 18, 2016Inventors: Sivashankar Krishnamoorthy, Krishna Kumar Manippady, Surani Bin Dolmanan, Kaixin Vivian Lin, Siew Lang Teo, Sudhiranjan Tripathy
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Patent number: 9202979Abstract: There is provided a method of fabricating a vertical light emitting diode which includes forming a light emitting diode structure. Forming the light emitting diode structure includes: forming a first material layer of a first conductivity type, forming a second material layer of a second conductivity type, forming a light emitting layer between the first material layer and the second material layer, and forming a plurality of generally ordered photonic nanostructures at a surface of the first material layer through which light generated from the light emitting layer is emitted for enhancing light extraction efficiency of the vertical light emitting diode. In particular, forming a plurality of generally ordered photonic nanostructures includes forming a self-assembled template including generally ordered nanoparticles on the surface of the first material layer to function as a mask for forming the photonic nanostructures at said surface of the first material layer.Type: GrantFiled: December 27, 2013Date of Patent: December 1, 2015Assignee: Agency for Science, Technology and ResearchInventors: Sivashankar Krishnamoorthy, Krishna Kumar Manippady, Surani Bin Dolmanan, Kaixin Vivian Lin, Siew Lang Teo, Sudhiranjan Tripathy
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Publication number: 20140183448Abstract: There is provided a method of fabricating a vertical light emitting diode which includes forming a light emitting diode structure. Forming the light emitting diode structure includes: forming a first material layer of a first conductivity type, forming a second material layer of a second conductivity type, forming a light emitting layer between the first material layer and the second material layer, and forming a plurality of generally ordered photonic nanostructures at a surface of the first material layer through which light generated from the light emitting layer is emitted for enhancing light extraction efficiency of the vertical light emitting diode. In particular, forming a plurality of generally ordered photonic nanostructures includes forming a self-assembled template including generally ordered nanoparticles on the surface of the first material layer to function as a mask for forming the photonic nanostructures at said surface of the first material layer.Type: ApplicationFiled: December 27, 2013Publication date: July 3, 2014Applicant: Agency for Science, Technology and ResearchInventors: Sivashankar Krishnamoorthy, Krishna Kumar Manippady, Surani Bin Dolmanan, Kaixin Vivian Lin, Siew Lang Teo, Sudhiranjan Tripathy
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Publication number: 20120267240Abstract: A photoelectrode including at least one polymer layer is provided. The at least one polymer layer defines the surface of the photoelectrode, or it defines an interlayer within the photoelectrode. The polymer layer can be made of a non-conductive polymer and have a thickness of 100 nm or less.Type: ApplicationFiled: October 26, 2010Publication date: October 25, 2012Applicant: Agency for Science Technology and ResearchInventors: Lin Ke, Surani Bin Dolmanan, Szu Cheng Lai