Patents by Inventor Suren A. Alexanian

Suren A. Alexanian has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Multi-level semiconductor memory architecture and method of forming the same
    Patent number: 7020001
    Abstract: An array block has at least two sub-array blocks and a first interconnect routing channel through which a first group of local interconnect lines extend. Each of the two sub-array blocks includes at least two lower-level sub-array blocks and a second interconnect routing channel through which a second group of local interconnect lines extend. The first group of local interconnect lines are configured to carry input information for accessing memory locations in which to store data or from which to retrieve data, and the second group of local interconnect lines are configured to carry a subset of the input information.
    Type: Grant
    Filed: October 7, 2004
    Date of Patent: March 28, 2006
    Assignee: Mosaic Systems, Inc.
    Inventor: Suren A. Alexanian
  • Multi-level semiconductor memory architecture and method of forming the same
    Publication number: 20050041513
    Abstract: An array block has at least two sub-array blocks and a first interconnect routing channel through which a first group of local interconnect lines extend. Each of the two sub-array blocks includes at least two lower-level sub-array blocks and a second interconnect routing channel through which a second group of local interconnect lines extend. The first group of local interconnect lines are configured to carry input information for accessing memory locations in which to store data or from which to retrieve data, and the second group of local interconnect lines are configured to carry a subset of the input information.
    Type: Application
    Filed: October 7, 2004
    Publication date: February 24, 2005
    Applicant: Mosaic Systems, Inc.
    Inventor: Suren Alexanian
  • Multi-level semiconductor memory architecture and method of forming the same
    Patent number: 6809947
    Abstract: An array block has at least two sub-array blocks and a first interconnect routing channel through which a first group of local interconnect lines extend. Each of the two sub-array blocks includes at least two lower-level sub-array blocks and a second interconnect routing channel through which a second group of local interconnect lines extend. The first group of local interconnect lines are configured to carry input information for accessing memory locations in which to store data or from which to retrieve data, and the second group of local interconnect lines are configured to carry a subset of the input information.
    Type: Grant
    Filed: March 6, 2003
    Date of Patent: October 26, 2004
    Assignee: Mosaic Systems, Inc.
    Inventor: Suren A. Alexanian
  • Multi-level semiconductor memory architecture and method of forming the same
    Publication number: 20030161203
    Abstract: An array block has at least two sub-array blocks and a first interconnect routing channel through which a first group of local interconnect lines extend. Each of the two sub-array blocks includes at least two lower-level sub-array blocks and a second interconnect routing channel through which a second group of local interconnect lines extend. The first group of local interconnect lines are configured to carry input information for accessing memory locations in which to store data or from which to retrieve data, and the second group of local interconnect lines are configured to carry a subset of the input information.
    Type: Application
    Filed: March 6, 2003
    Publication date: August 28, 2003
    Applicant: Mosaic Systems, Inc., a corporation of California
    Inventor: Suren A. Alexanian
  • High-speed low-power semiconductor memory architecture
    Patent number: 6567290
    Abstract: An array block has at least two sub-array blocks and a first interconnect routing channel through which a first group of local interconnect lines extend. Each of the two sub-array blocks includes at least two lower-level sub-array blocks and a second interconnect routing channel through which a second group of local interconnect lines extend. The first group of local interconnect lines are configured to carry input information for accessing memory locations in which to store data or from which to retrieve data, and the second group of local interconnect lines are configured to carry a subset of the input information.
    Type: Grant
    Filed: June 1, 2001
    Date of Patent: May 20, 2003
    Assignee: Mosaic Systems, Inc.
    Inventor: Suren A. Alexanian
  • High-speed low-power semiconductor memory architecture
    Publication number: 20020012262
    Abstract: An array block has at least two sub-array blocks and a first interconnect routing channel through which a first group of local interconnect lines extend. Each of the two sub-array blocks includes at least two lower-level sub-array blocks and a second interconnect routing channel through which a second group of local interconnect lines extend. The first group of local interconnect lines are configured to carry input information for accessing memory locations in which to store data or from which to retrieve data, and the second group of local interconnect lines are configured to carry a subset of the input information.
    Type: Application
    Filed: June 1, 2001
    Publication date: January 31, 2002
    Inventor: Suren A. Alexanian