Abstract: A pipelined central processor capable of executing both single-cycle instructions and multicycle instructions is provided. An instruction fetch stage of the processor includes an instruction cache memory and a prediction cache memory that are commonly addressed by a program counter register. The instruction cache memory stores instructions of a program being executed and microinstructions of a multicycle instruction interpreter. The prediction cache memory stores interpreter call predictions and interpreter entry addresses at the addresses of the multicycle intructions. When a call prediction occurs, the entry address of the instruction interpreter is loaded into the program counter register on the processing cycle immediately following the call prediction, and a return address is pushed onto a stack. The microinstructions of the interpreter are fetched sequentially from the instruction cache memory. When the interpreter is completed, the prediction cache memory makes a return prediction.

Abstract: A method and apparatus for radix-.beta. non-restoring division. The division process occurs in four phases. In a first phase, the input operands are transformed to produce a divisor lying in a designated numerical range. Next, a transitional phase involves generating an initial radix-.beta. quotient digit from the transformed numerator. An iterative phase of the process generates successive partial remainders according to a recursive method. From the sign and a single radix-.beta. digit of each of these partial remainders, the process generates a radix-.beta. quotient digit. Further, a fourth phase, which may run concurrently with the transitional and iterative phases, involves accumulating successively generated quotient digits to produce a final quotient value.

Abstract: A range transformation method for transforming the normalized divisor in a division calculation to a range wherein the transformed value differs from one by no more than the quantity 2.sup.-n. The method and apparatus generate the transform multiplier value from a first high order "q" digits of the divisor and generate an out-of-range indicator signal from at least those same digits. The thus generated multiplier value is modified in response to the out-of-range indicator signal when an out-of-range condition is indicated. The apparatus employs a read-only-memory for enabling the generation of the transform multiplier value without requiring either large table look-up storage or multiplicative functions. As a result, various division methods requiring an initial transformation to provide a divisor which approaches one in value can be efficiently implemented.