Patents by Inventor Suren Mohan

Suren Mohan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11538509
    Abstract: A compute-in-memory bitcell is provided that includes a pair of cross-coupled inverters for storing a stored bit. The compute-in-memory bitcell includes a logic gate formed by a pair of switches for multiplying the stored bit with an input vector bit. A controller controls the pair of switches responsive to a sign bit during a computation phase of operation and controls the pair of switches responsive to a magnitude bit during an execution phase of operation.
    Type: Grant
    Filed: March 17, 2021
    Date of Patent: December 27, 2022
    Assignee: QUALCOMM INCORPORATED
    Inventors: Seyed Arash Mirhaj, Ankit Srivastava, Sameer Wadhwa, Ren Li, Suren Mohan
  • Patent number: 11481881
    Abstract: Various embodiments of systems and methods for adaptive video subsampling for energy-efficient object detection are disclosed herein.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: October 25, 2022
    Assignee: Arizona Board of Regents on Behalf of Arizona State University
    Inventors: Andreas Spanias, Pavan Turaga, Sameeksha Katoch, Suren Jayasuriya, Divya Mohan
  • Publication number: 20220301605
    Abstract: A compute-in-memory bitcell is provided that includes a pair of cross-coupled inverters for storing a stored bit. The compute-in-memory bitcell includes a logic gate formed by a pair of switches for multiplying the stored bit with an input vector bit. A controller controls the pair of switches responsive to a sign bit during a computation phase of operation and controls the pair of switches responsive to a magnitude bit during an execution phase of operation.
    Type: Application
    Filed: March 17, 2021
    Publication date: September 22, 2022
    Inventors: Seyed Arash MIRHAJ, Ankit SRIVASTAVA, Sameer WADHWA, Ren LI, Suren MOHAN
  • Patent number: 11430493
    Abstract: A compute-in-memory bitcell is provided that includes a pair of cross-coupled inverters for storing a stored bit. The compute-in-memory bitcell includes a logic gate formed by a pair of switches for multiplying the stored bit with an input vector bit. A controller controls the pair of switches responsive to a sign bit during a computation phase of operation and controls the pair of switches responsive to a magnitude bit during an execution phase of operation.
    Type: Grant
    Filed: March 17, 2021
    Date of Patent: August 30, 2022
    Assignee: QUALCOMM INCORPORATED
    Inventors: Seyed Arash Mirhaj, Ankit Srivastava, Sameer Wadhwa, Ren Li, Suren Mohan
  • Patent number: 9929972
    Abstract: A method includes sending data from a first serial low-power inter-chip media bus (SLIMbus) component to a second SLIMbus component. The method further includes sending the data via at least a first SLIMbus data line of a plurality of SLIMbus data lines.
    Type: Grant
    Filed: December 13, 2012
    Date of Patent: March 27, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Hans Georg Gruber, Magesh Hariharan, Julio Arceo, Suren Mohan, Aris J. Balatsos
  • Patent number: 9065674
    Abstract: Methods, systems, apparatuses, and computer-readable media for controlling components connected to and/or otherwise associated with a data bus are presented. According to one or more aspects of the disclosure, a plurality of processing devices having data bus management capability and at least one data bus associated with the plurality of processing devices may be identified. Subsequently, an inter-processor communication (IPC) layer for communication between the plurality of processing devices and the at least one data bus may be established over a messaging layer utilized by the at least one data bus. At least one component associated with the at least one data bus may then be controlled via the IPC layer using at least one of the plurality of processing devices.
    Type: Grant
    Filed: January 17, 2012
    Date of Patent: June 23, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Hans Georg Gruber, Julio Arceo, Magesh Hariharan, Suren Mohan, Mark A. Landguth
  • Patent number: 9043634
    Abstract: Arrangements for restarting data transmission on a serial low-power inter-chip media bus (SLIMbus) are presented. A clock signal may be provided in an active mode to a component communicatively coupled with the SLIMbus. Immediately prior to the clock signal in the active mode being provided, the clock signal may have been in a paused mode. While the clock signal was in the paused mode at least until the clock signal is provided in the active mode, the data line may have been inactive (e.g., a toggle on the data line may not have been present). Frame synchronization data for a frame may be transmitted. The frame synchronization data for the frame, as received by the component, may not match expected frame synchronization data. Payload data may be transmitted as part of the frame to the component, wherein the payload data is expected to be read properly by the component.
    Type: Grant
    Filed: March 21, 2012
    Date of Patent: May 26, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Hans Georg Gruber, Julio Arceo, Magesh Hariharan, Suren Mohan
  • Patent number: 8667193
    Abstract: Techniques are disclosed for utilizing a non-ported generic device (NGD) or other non-ported hardware to couple processing device(s) to access components on a serial data bus without the need for integrated manager hardware. Using the NGD, a processing device(s) can utilize available unused bandwidth on the serial data bus to communicate with components coupled with the serial data bus, including a processing device having the manager hardware. Various alterations and embodiments are disclosed.
    Type: Grant
    Filed: October 25, 2011
    Date of Patent: March 4, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Hans Georg Gruber, Julio Arceo, Magesh Hariharan, Suren Mohan, Mark A. Landguth
  • Publication number: 20130019038
    Abstract: Methods, systems, apparatuses, and computer-readable media for controlling components connected to and/or otherwise associated with a data bus are presented. According to one or more aspects of the disclosure, a plurality of processing devices having data bus management capability and at least one data bus associated with the plurality of processing devices may be identified. Subsequently, an inter-processor communication (IPC) layer for communication between the plurality of processing devices and the at least one data bus may be established over a messaging layer utilized by the at least one data bus. At least one component associated with the at least one data bus may then be controlled via the IPC layer using at least one of the plurality of processing devices.
    Type: Application
    Filed: January 17, 2012
    Publication date: January 17, 2013
    Applicant: QUALCOMM Incorporated
    Inventors: Hans Georg Gruber, Julio Arceo, Magesh Hariharan, Suren Mohan, Mark A. Landguth
  • Publication number: 20120278646
    Abstract: Arrangements for restarting data transmission on a serial low-power inter-chip media bus (SLIMbus) are presented. A clock signal may be provided in an active mode to a component communicatively coupled with the SLIMbus. Immediately prior to the clock signal in the active mode being provided, the clock signal may have been in a paused mode. While the clock signal was in the paused mode at least until the clock signal is provided in the active mode, the data line may have been inactive (e.g., a toggle on the data line may not have been present). Frame synchronization data for a frame may be transmitted. The frame synchronization data for the frame, as received by the component, may not match expected frame synchronization data. Payload data may be transmitted as part of the frame to the component, wherein the payload data is expected to be read properly by the component.
    Type: Application
    Filed: March 21, 2012
    Publication date: November 1, 2012
    Applicant: QUALCOMM INCORPORATED
    Inventors: Hans Georg GRUBER, Julio ARCEO, Magesh HARIHARAN, Suren MOHAN
  • Publication number: 20120278518
    Abstract: Techniques are disclosed for utilizing a non-ported generic device (NGD) or other non-ported hardware to couple processing device(s) to access components on a serial data bus without the need for integrated manager hardware. Using the NGD, a processing device(s) can utilize available unused bandwidth on the serial data bus to communicate with components coupled with the serial data bus, including a processing device having the manager hardware. Various alterations and embodiments are disclosed.
    Type: Application
    Filed: October 25, 2011
    Publication date: November 1, 2012
    Applicant: QUALCOMM Incorporated
    Inventors: Hans Georg Gruber, Julio Arceo, Magesh Hariharan, Suren Mohan, Mark A. Landguth