Patents by Inventor Suren Mohan
Suren Mohan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11538509Abstract: A compute-in-memory bitcell is provided that includes a pair of cross-coupled inverters for storing a stored bit. The compute-in-memory bitcell includes a logic gate formed by a pair of switches for multiplying the stored bit with an input vector bit. A controller controls the pair of switches responsive to a sign bit during a computation phase of operation and controls the pair of switches responsive to a magnitude bit during an execution phase of operation.Type: GrantFiled: March 17, 2021Date of Patent: December 27, 2022Assignee: QUALCOMM INCORPORATEDInventors: Seyed Arash Mirhaj, Ankit Srivastava, Sameer Wadhwa, Ren Li, Suren Mohan
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Patent number: 11481881Abstract: Various embodiments of systems and methods for adaptive video subsampling for energy-efficient object detection are disclosed herein.Type: GrantFiled: June 15, 2020Date of Patent: October 25, 2022Assignee: Arizona Board of Regents on Behalf of Arizona State UniversityInventors: Andreas Spanias, Pavan Turaga, Sameeksha Katoch, Suren Jayasuriya, Divya Mohan
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Publication number: 20220301605Abstract: A compute-in-memory bitcell is provided that includes a pair of cross-coupled inverters for storing a stored bit. The compute-in-memory bitcell includes a logic gate formed by a pair of switches for multiplying the stored bit with an input vector bit. A controller controls the pair of switches responsive to a sign bit during a computation phase of operation and controls the pair of switches responsive to a magnitude bit during an execution phase of operation.Type: ApplicationFiled: March 17, 2021Publication date: September 22, 2022Inventors: Seyed Arash MIRHAJ, Ankit SRIVASTAVA, Sameer WADHWA, Ren LI, Suren MOHAN
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Patent number: 11430493Abstract: A compute-in-memory bitcell is provided that includes a pair of cross-coupled inverters for storing a stored bit. The compute-in-memory bitcell includes a logic gate formed by a pair of switches for multiplying the stored bit with an input vector bit. A controller controls the pair of switches responsive to a sign bit during a computation phase of operation and controls the pair of switches responsive to a magnitude bit during an execution phase of operation.Type: GrantFiled: March 17, 2021Date of Patent: August 30, 2022Assignee: QUALCOMM INCORPORATEDInventors: Seyed Arash Mirhaj, Ankit Srivastava, Sameer Wadhwa, Ren Li, Suren Mohan
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Patent number: 9929972Abstract: A method includes sending data from a first serial low-power inter-chip media bus (SLIMbus) component to a second SLIMbus component. The method further includes sending the data via at least a first SLIMbus data line of a plurality of SLIMbus data lines.Type: GrantFiled: December 13, 2012Date of Patent: March 27, 2018Assignee: QUALCOMM IncorporatedInventors: Hans Georg Gruber, Magesh Hariharan, Julio Arceo, Suren Mohan, Aris J. Balatsos
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Patent number: 9065674Abstract: Methods, systems, apparatuses, and computer-readable media for controlling components connected to and/or otherwise associated with a data bus are presented. According to one or more aspects of the disclosure, a plurality of processing devices having data bus management capability and at least one data bus associated with the plurality of processing devices may be identified. Subsequently, an inter-processor communication (IPC) layer for communication between the plurality of processing devices and the at least one data bus may be established over a messaging layer utilized by the at least one data bus. At least one component associated with the at least one data bus may then be controlled via the IPC layer using at least one of the plurality of processing devices.Type: GrantFiled: January 17, 2012Date of Patent: June 23, 2015Assignee: QUALCOMM IncorporatedInventors: Hans Georg Gruber, Julio Arceo, Magesh Hariharan, Suren Mohan, Mark A. Landguth
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Patent number: 9043634Abstract: Arrangements for restarting data transmission on a serial low-power inter-chip media bus (SLIMbus) are presented. A clock signal may be provided in an active mode to a component communicatively coupled with the SLIMbus. Immediately prior to the clock signal in the active mode being provided, the clock signal may have been in a paused mode. While the clock signal was in the paused mode at least until the clock signal is provided in the active mode, the data line may have been inactive (e.g., a toggle on the data line may not have been present). Frame synchronization data for a frame may be transmitted. The frame synchronization data for the frame, as received by the component, may not match expected frame synchronization data. Payload data may be transmitted as part of the frame to the component, wherein the payload data is expected to be read properly by the component.Type: GrantFiled: March 21, 2012Date of Patent: May 26, 2015Assignee: QUALCOMM IncorporatedInventors: Hans Georg Gruber, Julio Arceo, Magesh Hariharan, Suren Mohan
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Patent number: 8667193Abstract: Techniques are disclosed for utilizing a non-ported generic device (NGD) or other non-ported hardware to couple processing device(s) to access components on a serial data bus without the need for integrated manager hardware. Using the NGD, a processing device(s) can utilize available unused bandwidth on the serial data bus to communicate with components coupled with the serial data bus, including a processing device having the manager hardware. Various alterations and embodiments are disclosed.Type: GrantFiled: October 25, 2011Date of Patent: March 4, 2014Assignee: QUALCOMM IncorporatedInventors: Hans Georg Gruber, Julio Arceo, Magesh Hariharan, Suren Mohan, Mark A. Landguth
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Publication number: 20130019038Abstract: Methods, systems, apparatuses, and computer-readable media for controlling components connected to and/or otherwise associated with a data bus are presented. According to one or more aspects of the disclosure, a plurality of processing devices having data bus management capability and at least one data bus associated with the plurality of processing devices may be identified. Subsequently, an inter-processor communication (IPC) layer for communication between the plurality of processing devices and the at least one data bus may be established over a messaging layer utilized by the at least one data bus. At least one component associated with the at least one data bus may then be controlled via the IPC layer using at least one of the plurality of processing devices.Type: ApplicationFiled: January 17, 2012Publication date: January 17, 2013Applicant: QUALCOMM IncorporatedInventors: Hans Georg Gruber, Julio Arceo, Magesh Hariharan, Suren Mohan, Mark A. Landguth
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Publication number: 20120278646Abstract: Arrangements for restarting data transmission on a serial low-power inter-chip media bus (SLIMbus) are presented. A clock signal may be provided in an active mode to a component communicatively coupled with the SLIMbus. Immediately prior to the clock signal in the active mode being provided, the clock signal may have been in a paused mode. While the clock signal was in the paused mode at least until the clock signal is provided in the active mode, the data line may have been inactive (e.g., a toggle on the data line may not have been present). Frame synchronization data for a frame may be transmitted. The frame synchronization data for the frame, as received by the component, may not match expected frame synchronization data. Payload data may be transmitted as part of the frame to the component, wherein the payload data is expected to be read properly by the component.Type: ApplicationFiled: March 21, 2012Publication date: November 1, 2012Applicant: QUALCOMM INCORPORATEDInventors: Hans Georg GRUBER, Julio ARCEO, Magesh HARIHARAN, Suren MOHAN
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Publication number: 20120278518Abstract: Techniques are disclosed for utilizing a non-ported generic device (NGD) or other non-ported hardware to couple processing device(s) to access components on a serial data bus without the need for integrated manager hardware. Using the NGD, a processing device(s) can utilize available unused bandwidth on the serial data bus to communicate with components coupled with the serial data bus, including a processing device having the manager hardware. Various alterations and embodiments are disclosed.Type: ApplicationFiled: October 25, 2011Publication date: November 1, 2012Applicant: QUALCOMM IncorporatedInventors: Hans Georg Gruber, Julio Arceo, Magesh Hariharan, Suren Mohan, Mark A. Landguth