Patents by Inventor Surena Neshvad

Surena Neshvad has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus for improving high availability in a PCI express link through predictive failure analysis
    Patent number: 7836352
    Abstract: A method and apparatus is described herein for tracking errors for one of a plurality of lanes in a link, tracking errors for the link, and in the case of a root complex, tracking error correction messages. This information is used to determine the suitability for use of a lane and to determine if correction action is needed. In one embodiment, this method and apparatus is used with PCI Express interconnects.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: November 16, 2010
    Assignee: Intel Corporation
    Inventors: Debendra Das Sharma, Surena Neshvad, Guru Rajamani, Hanh Hoang
  • Method and apparatus for improving high availability in a PCI express link through predictive failure analysis
    Publication number: 20080005706
    Abstract: A method and apparatus is described herein for tracking errors for one of a plurality of lanes in a link, tracking errors for the link, and in the case of a root complex, tracking error correction messages. This information is used to determine the suitability for use of a lane and to determine if correction action is needed. In one embodiment, this method and apparatus is used with PCI Express interconnects.
    Type: Application
    Filed: June 30, 2006
    Publication date: January 3, 2008
    Inventors: Debendra Das Sharma, Surena Neshvad, Guru Rajamani, Hanh Hoang