Patents by Inventor Surendra DESHMUKH

Surendra DESHMUKH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Write assist circuit for static random-access memory (SRAM)
    Patent number: 12205636
    Abstract: A write assist circuit includes a first power control circuit and second power control circuit, each comprising a first switch and second switch. The first switch of first power control circuit has first drive strength and is configured to be controlled by a column select line, a power control line, a first bit line, and a power supply. The first switch of the second power control circuit has the first drive strength and is configured to be controlled by the column select line, the power control line, a second bit line, and the power supply. The second switch has a second drive strength and is configured to be controlled by the power control line. The first switches are configured to be controlled using input data on first- and second-bit line, respectively, for altering power supply to first inverter and second inverter of SRAM bitcell.
    Type: Grant
    Filed: February 2, 2023
    Date of Patent: January 21, 2025
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Poornima Venkatasubramanian, Pushp Khatter, Lava Kumar Pulluru, Manish Chandra Joshi, Ved Prakash, Anurag Kumar, Surendra Deshmukh
  • WRITE ASSIST CIRCUIT FOR STATIC RANDOM-ACCESS MEMORY (SRAM)
    Publication number: 20240161821
    Abstract: A write assist circuit includes a first power control circuit and second power control circuit, each comprising a first switch and second switch. The first switch of first power control circuit has first drive strength and is configured to be controlled by a column select line, a power control line, a first bit line, and a power supply. The first switch of the second power control circuit has the first drive strength and is configured to be controlled by the column select line, the power control line, a second bit line, and the power supply. The second switch has a second drive strength and is configured to be controlled by the power control line. The first switches are configured to be controlled using input data on first- and second-bit line, respectively, for altering power supply to first inverter and second inverter of SRAM bitcell.
    Type: Application
    Filed: February 2, 2023
    Publication date: May 16, 2024
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Poornima VENKATASUBRAMANIAN, Pushp KHATTER, Lava Kumar PULLURU, Manish Chandra JOSHI, Ved PRAKASH, Anurag KUMAR, Surendra DESHMUKH