Patents by Inventor Surendra Paravada

Surendra Paravada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240160576
    Abstract: Methods that may be performed by a host controller of a computing device for synchronizing logical-to-physical (L2P) tables before entering a hibernate mode are disclosed. Embodiment methods may include determining whether a first L2P table stored in a dynamic random-access memory (DRAM) communicatively connected to the host controller is out of synchronization with a second L2P table stored in a static random-access memory (SRAM) of a universal flash storage (UFS) device communicatively connected to the host controller via a link. If the first and second L2P tables are out of synch, the host controller may retrieve at least one modified L2P map entry from the second L2P table when the UFS device is configured to enter a hibernate mode from the UFS device, and update the first L2P tabled with the at least one modified L2P map entry before the link and the UFS device enter the hibernate mode.
    Type: Application
    Filed: November 10, 2022
    Publication date: May 16, 2024
    Inventors: Madhu Yashwanth BOENAPALLI, Surendra PARAVADA, Sai Praneeth SREERAM
  • Patent number: 11966341
    Abstract: Methods that may be performed by a host controller of a computing device for synchronizing logical-to-physical (L2P) tables before entering a hibernate mode are disclosed. Embodiment methods may include determining whether a first L2P table stored in a dynamic random-access memory (DRAM) communicatively connected to the host controller is out of synchronization with a second L2P table stored in a static random-access memory (SRAM) of a universal flash storage (UFS) device communicatively connected to the host controller via a link. If the first and second L2P tables are out of synch, the host controller may retrieve at least one modified L2P map entry from the second L2P table when the UFS device is configured to enter a hibernate mode from the UFS device, and update the first L2P tabled with the at least one modified L2P map entry before the link and the UFS device enter the hibernate mode.
    Type: Grant
    Filed: November 10, 2022
    Date of Patent: April 23, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Madhu Yashwanth Boenapalli, Surendra Paravada, Sai Praneeth Sreeram
  • Patent number: 11800342
    Abstract: A method may involve receiving fingerprint sensor data from a fingerprint sensor system, detecting, according to the fingerprint sensor data, a presence of a digit on an outer surface of the apparatus in a fingerprint sensor system area; determining, according to the fingerprint sensor data, a digit force or a digit pressure of the digit on the outer surface of the apparatus; and making, according to the fingerprint sensor data, a time threshold determination. The time threshold determination may involve determining whether a length of time during which the digit force exceeds a threshold digit force or during which the digit pressure exceeds a threshold digit pressure is greater than or equal to a threshold length of time. The method may involve determining, based at least in part on the time threshold determination, whether to enable one or more emergency response functions of the apparatus.
    Type: Grant
    Filed: September 20, 2021
    Date of Patent: October 24, 2023
    Assignee: QUALCOMM Incorporated
    Inventors: Sai Praneeth Sreeram, Surendra Paravada, Madhu Yashwanth Boenapalli, Bipul Tarafdar
  • Patent number: 11782837
    Abstract: Systems and methods for fast memory access are disclosed. In one aspect, a processor such as, for example, a control circuit in a system on a chip (SoC) that couples to an external memory such as, for example a Universal File System (UFS) memory (e.g., a NAND flash memory) with a partial logical to physical (L2P) mapping table stored in the external memory as well as a local L2P mapping table stored in a local memory (e.g., dynamic random-access memory (DRAM)). The control circuit may evaluate what percentage of entries in the local L2P mapping table are active compared to inactive. If the number of inactive exceeds the number of active, the control circuit may send a read command without accessing the local L2P mapping table.
    Type: Grant
    Filed: November 4, 2021
    Date of Patent: October 10, 2023
    Assignee: QUALCOMM Incorporated
    Inventors: Madhu Yashwanth Boenapalli, Sai Praneeth Sreeram, Surendra Paravada
  • Publication number: 20230134404
    Abstract: Systems and methods for fast memory access are disclosed. In one aspect, a processor such as, for example, a control circuit in a system on a chip (SoC) that couples to an external memory such as, for example a Universal File System (UFS) memory (e.g., a NAND flash memory) with a partial logical to physical (L2P) mapping table stored in the external memory as well as a local L2P mapping table stored in a local memory (e.g., dynamic random-access memory (DRAM)). The control circuit may evaluate what percentage of entries in the local L2P mapping table are active compared to inactive. If the number of inactive exceeds the number of active, the control circuit may send a read command without accessing the local L2P mapping table.
    Type: Application
    Filed: November 4, 2021
    Publication date: May 4, 2023
    Inventors: Madhu Yashwanth Boenapalli, Sai Praneeth Sreeram, Surendra Paravada
  • Publication number: 20230085885
    Abstract: A method may involve receiving fingerprint sensor data from a fingerprint sensor system, detecting, according to the fingerprint sensor data, a presence of a digit on an outer surface of the apparatus in a fingerprint sensor system area; determining, according to the fingerprint sensor data, a digit force or a digit pressure of the digit on the outer surface of the apparatus; and making, according to the fingerprint sensor data, a time threshold determination. The time threshold determination may involve determining whether a length of time during which the digit force exceeds a threshold digit force or during which the digit pressure exceeds a threshold digit pressure is greater than or equal to a threshold length of time. The method may involve determining, based at least in part on the time threshold determination, whether to enable one or more emergency response functions of the apparatus.
    Type: Application
    Filed: September 20, 2021
    Publication date: March 23, 2023
    Inventors: Sai Praneeth Sreeram, Surendra Paravada, Madhu Yashwanth Boenapalli, Bipul Tarafdar
  • Patent number: 11275620
    Abstract: A method of shuffling turbo-write buffers of a universal flash storage system is described. The method includes periodically determining a performance index of each turbo-write buffer allocated to a unique logical unit number of the universal flash storage system. The method also includes shifting a position of at least two of the turbo-write buffers according to the performance index of each of the turbo-write buffers and a threshold performance level.
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: March 15, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Madhu Yashwanth Boenapalli, Surendra Paravada, Sai Praneeth Sreeram
  • Publication number: 20210294654
    Abstract: A method of shuffling turbo-write buffers of a universal flash storage system is described. The method includes periodically determining a performance index of each turbo-write buffer allocated to a unique logical unit number of the universal flash storage system. The method also includes shifting a position of at least two of the turbo-write buffers according to the performance index of each of the turbo-write buffers and a threshold performance level.
    Type: Application
    Filed: March 19, 2020
    Publication date: September 23, 2021
    Inventors: Madhu Yashwanth BOENAPALLI, Surendra PARAVADA, Sai Praneeth SREERAM
  • Publication number: 20210263720
    Abstract: Systems and methods for flash memory conflict avoidance cause a firmware over the air (FOTA) update to be given priority over a scrubbing operation unless the memory element meets or exceeds a predefined health degradation parameter. When the memory element meets or exceeds the predefined health degradation parameter, the scrubbing operation is given priority over the FOTA update. By enforcing these priorities, scrubbing and FOTA updates do not occur at the same time and conflicts are thereby avoided. Since conflicts are avoided, the chance of memory corruption is decreased and the chance of “bricking” the computing device is likewise decreased.
    Type: Application
    Filed: February 24, 2020
    Publication date: August 26, 2021
    Inventors: Madhu Yashwanth Boenapalli, Sai Praneeth Sreeram, Surendra Paravada, Venu Madhav Mokkapati
  • Patent number: 11048438
    Abstract: In some aspects, the present disclosure provides a method for managing data communication rates of a memory device. The method includes receiving an input/output (I/O) operation to be performed by the memory device, detecting a temperature of the memory device, and determining whether the detected temperature satisfies a threshold condition. The threshold condition is satisfied if the detected temperature is above a first temperature threshold or below a second temperature threshold. If the threshold condition is satisfied, selecting a gear from a plurality of gears based on a ranking of the plurality of gears at the detected temperature, wherein each gear of the plurality of gears correspond to a respective one of a plurality of data rates used by the memory device for performing I/O operations, and serving, to the memory device, the I/O operation with an indication to perform the I/O operation using the selected gear.
    Type: Grant
    Filed: May 1, 2019
    Date of Patent: June 29, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Madhu Yashwanth Boenapalli, Sai Praneeth Sreeram, Surendra Paravada, Venu Madhav Mokkapati
  • Publication number: 20210117127
    Abstract: In some aspects, the present disclosure provides a method for managing a command queue in a universal flash storage (UFS) host device. The method includes receiving, by a host controller, a plurality of memory commands from a UFS driver, storing, by the host controller, the plurality of memory commands in a command queue, and determining, by the host controller, whether the plurality of memory commands comprises a contiguous set of commands, where a number of the contiguous set of commands is greater than a threshold number of commands, and where each command of the contiguous set of commands has a priority less than a threshold priority.
    Type: Application
    Filed: October 16, 2019
    Publication date: April 22, 2021
    Inventors: Madhu Yashwanth BOENAPALLI, Sai Praneeth SREERAM, Surendra PARAVADA, Venu Madhav MOKKAPATI
  • Publication number: 20210109674
    Abstract: In some aspects, the present disclosure provides a method for managing memory commands from a plurality of masters. The method includes receiving, at a storage driver, a plurality of memory commands from the plurality of masters and determining, by the storage driver, a number of command queues of a plurality of command queues to use to service the plurality of memory commands. In certain aspects, the method includes routing, via one or more of a plurality of lanes, the plurality of memory commands to a storage controller according to the determined number of command queues, wherein each of the plurality of lanes corresponds to one of the plurality of command queues and storing, by the storage controller, one or more of the plurality of memory commands in each of the determined number of command queues.
    Type: Application
    Filed: October 15, 2019
    Publication date: April 15, 2021
    Inventors: Madhu Yashwanth BOENAPALLI, Surendra PARAVADA, Venu Madhav MOKKAPATI, Sai Praneeth SREERAM
  • Publication number: 20200348884
    Abstract: In some aspects, the present disclosure provides a method for managing data communication rates of a memory device. The method includes receiving an input/output (I/O) operation to be performed by the memory device, detecting a temperature of the memory device, and determining whether the detected temperature satisfies a threshold condition. The threshold condition is satisfied if the detected temperature is above a first temperature threshold or below a second temperature threshold. If the threshold condition is satisfied, selecting a gear from a plurality of gears based on a ranking of the plurality of gears at the detected temperature, wherein each gear of the plurality of gears correspond to a respective one of a plurality of data rates used by the memory device for performing I/O operations, and serving, to the memory device, the I/O operation with an indication to perform the I/O operation using the selected gear.
    Type: Application
    Filed: May 1, 2019
    Publication date: November 5, 2020
    Inventors: Madhu Yashwanth BOENAPALLI, Sai Praneeth SREERAM, Surendra PARAVADA, Venu Madhav MOKKAPATI
  • Patent number: 10769079
    Abstract: In a conventional system with a UFS storage device connected to a UFS host over one or more lanes, the lanes can support different transmission speeds, referred to as gears. The UFS host shifts lanes and gears based on the type of request it receives. When the requests arrive in random order of gear requirements, the frequent shifting of the lanes and gears causes significant power consumption. To address this issue, it is proposed to implement a queue-based shifting in which arriving requests may be queued based on their gear requirements. When a queue is selected, multiple requests in the selected queue, which are all of same or similar gear requirement, can be served. This can reduce the frequency of gear shifting, and hence reduce power consumption.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: September 8, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Madhu Yashwanth Boenapalli, Venu Madhav Mokkapati, Surendra Paravada
  • Patent number: 10762336
    Abstract: Certain aspects of the present disclosure provide techniques for performing face recognition in low light conditions using an electronic device. One aspect provides a method including determining if a brightness level within a viewing area of the electronic device satisfies a threshold. The method includes increasing a luminance output of the electronic device from a first luminance level to a second luminance level when the brightness level does not satisfy the threshold. The method includes capturing an image at the second luminance level when the brightness level does not satisfy the threshold. The method includes capturing the image at the first luminance level when the brightness level satisfies the threshold. The method includes detecting a face in the image. The method includes determining if the face corresponds to an authorized user. The method includes unlocking the electronic device when the face corresponds to an authorized user.
    Type: Grant
    Filed: May 1, 2018
    Date of Patent: September 1, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Madhu Yashwanth Boenapalli, Venu Madhav Mokkapati, Surendra Paravada
  • Patent number: 10725706
    Abstract: A method of scheduling universal flash storage (UFS) operations using a refresh handover mechanism is described. The method includes receiving, during refresh of a UFS device, a request for an input/output (I/O) operation. The method also includes handing over between a first type of refresh operation and a second type of refresh operation in response to the request for the I/O operation.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: July 28, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Madhu Yashwanth Boenapalli, Hyunsuk Shin, Surendra Paravada, Sai Praneeth Sreeram, Venu Madhav Mokkapati
  • Publication number: 20200233605
    Abstract: A method of scheduling universal flash storage (UFS) operations using a refresh handover mechanism is described. The method includes receiving, during refresh of a UFS device, a request for an input/output (I/O) operation. The method also includes handing over between a first type of refresh operation and a second type of refresh operation in response to the request for the I/O operation.
    Type: Application
    Filed: January 23, 2019
    Publication date: July 23, 2020
    Inventors: Madhu Yashwanth BOENAPALLI, Hyunsuk SHIN, Surendra PARAVADA, Sai Praneeth SREERAM, Venu Madhav MOKKAPATI
  • Publication number: 20190340421
    Abstract: Certain aspects of the present disclosure provide techniques for performing face recognition in low light conditions using an electronic device. One aspect provides a method including determining if a brightness level within a viewing area of the electronic device satisfies a threshold. The method includes increasing a luminance output of the electronic device from a first luminance level to a second luminance level when the brightness level does not satisfy the threshold. The method includes capturing an image at the second luminance level when the brightness level does not satisfy the threshold. The method includes capturing the image at the first luminance level when the brightness level satisfies the threshold. The method includes detecting a face in the image. The method includes determining if the face corresponds to an authorized user. The method includes unlocking the electronic device when the face corresponds to an authorized user.
    Type: Application
    Filed: May 1, 2018
    Publication date: November 7, 2019
    Inventors: Madhu Yashwanth BOENAPALLI, Venu Madhav MOKKAPATI, Surendra PARAVADA
  • Publication number: 20190304552
    Abstract: An embodiment is directed to an apparatus that comprises a host controller and a flash memory. The host controller monitors a temperature in a first memory block of the flash memory (e.g., based on a reported temperature measurements from the flash memory), and selectively synchronizes a first refresh of the first memory block with a second refresh of a second memory block of the flash memory based in part upon the monitored temperature. For example, an immediate refresh of the first memory block may be performed if there is a pending I/O request for the first memory block, an error rate associated with the first memory block exceeds an error rate threshold and/or the monitored temperature of the first memory block exceeds a temperature threshold; otherwise, a synchronized refresh of the first and second memory blocks may be executed.
    Type: Application
    Filed: March 30, 2018
    Publication date: October 3, 2019
    Inventors: Madhu Yashwanth BOENAPALLI, Surendra PARAVADA, Sai Praneeth SREERAM, Venu Madhav MOKKAPATI
  • Publication number: 20190303313
    Abstract: In a conventional system with a UFS storage device connected to a UFS host over one or more lanes, the lanes can support different transmission speeds, referred to as gears. The UFS host shifts lanes and gears based on the type of request it receives. When the requests arrive in random order of gear requirements, the frequent shifting of the lanes and gears causes significant power consumption. To address this issue, it is proposed to implement a queue-based shifting in which arriving requests may be queued based on their gear requirements. When a queue is selected, multiple requests in the selected queue, which are all of same or similar gear requirement, can be served. This can reduce the frequency of gear shifting, and hence reduce power consumption.
    Type: Application
    Filed: March 27, 2018
    Publication date: October 3, 2019
    Inventors: Madhu Yashwanth BOENAPALLI, Venu Madhav MOKKAPATI, Surendra PARAVADA