Abstract: This disclosure provides systems, methods, and devices for dynamic power management of automotive embedded systems in vehicles. In a first aspect, a method includes determining, by a processor, a vehicle ignition frequency of an automotive embedded system of a vehicle; determining, by the processor, an occupancy rate of a dynamic memory of the automotive embedded system; determining, by the processor, based on the vehicle ignition frequency and the occupancy rate, a power management mode for the automotive embedded system; and configuring, by the processor, the automotive embedded system based on the power management mode. Other aspects and features are also claimed and described.

Abstract: Systems and methods are provided for enhancing the endurance of a Universal Flash Storage (UFS) device by providing a UFS pinned region relocation mechanism that relocates the UFS pinned region of the write booster buffer to a portion of the write booster buffer that was previously part of a non-pinned region of the write booster buffer based on an indication of the health of the UFS pinned region.

Abstract: This disclosure provides methods, components, devices, and systems for providing remote authentication information exchange for a system service in a secure device ecosystem. Some aspects more specifically relate to exchanging credential information between two devices in the secure device ecosystem, including manually entered passwords and stored credentials such as stored biometric credentials. Remote credential information exchanged between the two devices is provided to a system service on one of the devices by updating missing credential information using the remote credential information.

Abstract: Systems and methods are provided for enhancing Universal Flash storage (UFS) power mode transitions by autonomously entering the sleep or power down states upon the expiration of a timer, thereby eliminating the need to reactivate the link between the UFS host and the UFS device to send sleep or power down commands from the UFS host to the UFS device. Eliminating the need to frequently reactivate the link to transition it into sleep and power down states reduces power consumption associated with reactivating the link and keeping it in the active state while the sleep and power commands are transmitted by the UFS host and responded to by the UFS device. In addition, eliminating the need to frequently reactivate the link and keep it active for these purposes reduces latencies associated with issuing the sleep and power down commands.

Abstract: In a flash memory device, portions of a write buffer may be merged into a user space logical unit based on a measurement of write buffer usage. In a Universal Flash Storage (UFS) device configured with the WriteBooster feature, the write buffer may be a WriteBooster buffer. When it is determined that a user space logical unit has become full, then the write buffer usage may be determined. Portions of the write buffer that are least used or have the longest remaining lifetime may be preferentially merged into the user space logical unit.

Abstract: A system and method reduce bootup latency in systems that run Auto operating systems (Auto OS). When, or just prior to, the system controller initiating suspend-to-disk (S2D) process entry, the system controller causes a memory controller to determine the percentage of volatile memory that is currently occupied and compares that percentage of occupancy to a predetermined threshold (TH) percentage. If the percentage of occupancy exceeds the predetermined TH percentage, then the memory controller tags apps that are occupying volatile memory as either background apps or foreground apps, terminates the background apps, clears volatile memory of any instructions and data associated with the terminated background apps, takes a snapshot of the state of volatile memory after the terminated background apps and associated data have been cleared, and saves the snapshot to a designated storage location in nonvolatile memory before entering hibernate mode.

Abstract: In a flash memory device, portions of a write buffer may be merged into a user space logical unit based on a measurement of write buffer usage. In a Universal Flash Storage (UFS) device configured with the WriteBooster feature, the write buffer may be a WriteBooster buffer. When it is determined that a user space logical unit has become full, then the write buffer usage may be determined. Portions of the write buffer that are least used or have the longest remaining lifetime may be preferentially merged into the user space logical unit.

Abstract: Methods that may be performed by a host controller of a computing device for host performance booster (HPB) mode management. Embodiments may include enabling an HPB mode based on availability of the host controller and availability of a memory device controller. In some embodiments, enabling the HPB mode based on the availability of the host controller and the availability of the memory device controller may include enabling a device control mode in response to an operating state of the host controller being busy and an operating state of the memory device controller being available. In some embodiments, enabling the HPB mode based on the availability of the host controller and the availability of the memory device controller may include enabling a host control mode in response to the operating state of the host controller being available and the operating state of the memory device controller being busy.

Abstract: This disclosure provides systems, methods, and devices for memory systems that support improved power state transition. In a first aspect, a method of accessing data in a flash memory system includes a controller configured to perform operations including: determining a power state transition of the memory system to a non-operational power state; determining, after determining the power state transition, whether a current power state is a higher-power state than a threshold power state; and transmitting, after determining the current power state is the higher-power state than the threshold power state, a first command to the memory system to transition to the threshold power state before the memory system transitions to the non-operational power state. Other aspects and features are also claimed and described.

Abstract: This disclosure provides methods, components, devices, and systems for providing remote authentication information exchange for a system service in a secure device ecosystem. Some aspects more specifically relate to exchanging credential information between two devices in the secure device ecosystem, including manually entered passwords and stored credentials such as stored biometric credentials. Remote credential information exchanged between the two devices is provided to a system service on one of the devices by updating missing credential information using the remote credential information.

Abstract: A Peripheral Component Interconnect Express (PCIe) system and method achieve reduced latency and improved performance by reconfiguring the PCIe link to use an increased number of lanes for retransmitting data packets held in a replay buffer if one or more data packets transmitted by the TX device are flagged as not acknowledged (NACK) by the RX device. Before retransmitting the NACK-flagged packet(s), the link is reconfigured to use a greater number of lanes, preferably the maximum number of lanes that are available for use, and then the NACK-flagged packet(s) is retransmitted using the greater number of lanes until successful receipt of the NACK-flagged packets has been acknowledged by the RX device. Once the NACK-flagged packet(s) is successfully received by the RX device, the link is reconfigured to use the previous number of lanes and operations of the link resume using the previous number of lanes.

Abstract: A Peripheral Component Interconnect Express (PCIe) system and method achieve reduced power consumption and latency. When the link transitions from an active functional state in which the link has a first configuration of N active lanes to a power-saving state, the number of active lanes is collapsed such that M of the N lanes are maintained in an active power-saving state and P of the N lanes are maintained in an electrically idle state, where M, N and P are positive integers and N>P>M. The reduction in lane width reduces power consumption. Bit values specifying the current link configuration can be saved in a control register and read and compared to bit values contained in a link control register before transitioning back to the active functional state. If the bit values match, the active functional state is resumed directly from the recovery state, thereby reducing latency.

Abstract: A host device includes a memory configured to store a logical-to-physical address mapping table of a flash memory device. The host device also includes one or more processors coupled to the memory and configured to be coupled to the flash memory device. The one or more processors are configured to determine whether a trigger condition is satisfied. The trigger condition is associated with checking a distribution of write data that is written to the flash memory device. The one or more processors are also configured to, based on a determination that the trigger condition is satisfied, identify a die of the flash memory device that has a higher data occupancy than at least one other die of the flash memory device, and send a command to the flash memory device to move data from the identified die to one or more other dies of the flash memory device.

Abstract: This disclosure provides systems, methods, and devices for memory systems that support packed commands for improved performance and reduced power consumption. In a first aspect, a method of accessing data in a flash memory system includes a host memory controller receiving a plurality of commands from a storage driver for execution by a flash memory device; packaging, by the memory controller of the host device, the plurality of commands as a packed command in a packet; and transmitting, by the memory controller of the host device to the flash memory device, the packet comprising the packed command for execution by the flash memory device. The use of packed commands may be based on determining the command acknowledgement delay from the flash memory device exceeds a threshold delay. Other aspects and features are also claimed and described.

Abstract: A Peripheral Component Interconnect Express (PCIe) system is configured to determine when the frequency of link speed switching needed to service incoming and upcoming client requests is too high. The system is also configured to determine a modest link speed to be used to service incoming and upcoming client requests in cases where the link speed switching that will be needed is too high and causes the incoming and upcoming client requests to be serviced at the modest link speed instead of at the link speeds associated with the predefined BWs of the clients. By doing this when the frequency of link speed switching needed is too high, the PCIe system achieves better throughput while also reducing power consumption.

Abstract: This disclosure provides systems, methods, and devices for memory systems that support enhanced write buffer flush schemes. In a first aspect, a method performed by a memory controller includes maintaining a list of data segments stored in a write buffer having a single-level cell memory architecture. The list includes, for each entry of the list, a data segment identifier of a respective data segment and an available contiguous memory space in the write buffer if the data segment is flushed. The list is sorted based on the available contiguous memory space. The method includes detecting a flush opportunity and initiating, based on the detecting, a flush operation to write a first data segment that corresponds to a first entry of the list from the write buffer to a memory module having a higher storage density memory architecture. Other aspects and features are also claimed and described.

Abstract: This disclosure provides systems, methods, and devices for memory systems that support enhanced write buffer flush schemes. In a first aspect, a method performed by a memory controller includes maintaining a list of data segments stored in a write buffer having a single-level cell memory architecture. The list includes, for each entry of the list, a data segment identifier of a respective data segment and an available contiguous memory space in the write buffer if the data segment is flushed. The list is sorted based on the available contiguous memory space. The method includes detecting a flush opportunity and initiating, based on the detecting, a flush operation to write a first data segment that corresponds to a first entry of the list from the write buffer to a memory module having a higher storage density memory architecture. Other aspects and features are also claimed and described.

Abstract: A host device includes a memory configured to store a logical-to-physical address mapping table of a flash memory device. The host device also includes one or more processors coupled to the memory and configured to be coupled to the flash memory device. The one or more processors are configured to determine whether a trigger condition is satisfied. The trigger condition is associated with checking a distribution of write data that is written to the flash memory device. The one or more processors are also configured to, based on a determination that the trigger condition is satisfied, identify a die of the flash memory device that has a higher data occupancy than at least one other die of the flash memory device, and send a command to the flash memory device to move data from the identified die to one or more other dies of the flash memory device.

Abstract: A system and method reduce bootup latency in systems that run Auto operating systems (Auto OS). When, or just prior to, the system controller initiating suspend-to-disk (S2D) process entry, the system controller causes a memory controller to determine the percentage of volatile memory that is currently occupied and compares that percentage of occupancy to a predetermined threshold (TH) percentage. If the percentage of occupancy exceeds the predetermined TH percentage, then the memory controller tags apps that are occupying volatile memory as either background apps or foreground apps, terminates the background apps, clears volatile memory of any instructions and data associated with the terminated background apps, takes a snapshot of the state of volatile memory after the terminated background apps and associated data have been cleared, and saves the snapshot to a designated storage location in nonvolatile memory before entering hibernate mode.

Abstract: Methods that may be performed by a universal flash storage (UFS) system of a computing device for updating logical-to-physical (L2P) address mapping tables. Various embodiments may include enabling a device control mode (DCM) of host performance booster (HPB) based on a flush of a writebooster buffer to a normal storage of a UFS device of the UFS system, and updating an L2P address mapping table at a host device of the UFS system while DCM is enabled based on the flush of the writebooster buffer to the normal storage. Some embodiments may include generating a signal having an indicator of a UFS protocol information unit configured to indicate a change in an HPB mode at the UFS device based on the flush of the writebooster buffer to the normal storage, and sending the signal from the UFS device to the host device.