Patents by Inventor Surendra Singh RAWAT

Surendra Singh RAWAT has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11568117
    Abstract: A system and method for generating simulation-friendly compact physical models for passive structures is disclosed. The method includes generating an impedance map specifying impedances at a plurality of frequencies corresponding to one or more port-pairs of a circuit component using a processor to extract a plurality of impedance values between the one or more port-pairs based on a first value for each parameter of a plurality of parameters of the circuit component. The method includes generating a second circuit representation model based on updating the plurality of impedance values between the one or more port-pairs based on a second value for one or more parameters of the plurality of parameters of the circuit component, and updating the second circuit representation model by tuning the updated plurality of impedance values of the between the one or more port-pairs based on a predetermined use context of the circuit component in a circuit.
    Type: Grant
    Filed: March 9, 2021
    Date of Patent: January 31, 2023
    Assignee: SYNOPSYS, INC.
    Inventors: Surendra Singh Rawat, Sunderarajan S. Mohan
  • Publication number: 20210279395
    Abstract: A system and method for generating simulation-friendly compact physical models for passive structures is disclosed. The method includes generating an impedance map specifying impedances at a plurality of frequencies corresponding to one or more port-pairs of a circuit component using a processor to extract a plurality of impedance values between the one or more port-pairs based on a first value for each parameter of a plurality of parameters of the circuit component. The method includes generating a second circuit representation model based on updating the plurality of impedance values between the one or more port-pairs based on a second value for one or more parameters of the plurality of parameters of the circuit component, and updating the second circuit representation model by tuning the updated plurality of impedance values of the between the one or more port-pairs based on a predetermined use context of the circuit component in a circuit.
    Type: Application
    Filed: March 9, 2021
    Publication date: September 9, 2021
    Applicant: Synopsys, Inc.
    Inventors: Surendra Singh RAWAT, Sunderarajan S. MOHAN