Abstract: Systems and methods for displaying search item scores and related information for easier search result selection. In one aspect, the method includes receiving a search request for a software component, retrieving a programming language information of the software component, retrieving an ecosystem information of the software component, retrieving a licensing information of the software component, retrieving a quality score of the software component, retrieving a security score of the software component, retrieving details of sources and associated details of the software component, dynamically generating a results information widget including information associated with the software component, and searching, based on the retrieved information, internet sources to assimilate associated information of the software components.

Abstract: An apparatus includes a control circuit configured to selectively activate, based on an operating mode signal, either a local clock signal or a pulse signal. The apparatus further includes a data storage circuit that is coupled to a data signal, the local clock signal, and the pulse signal. The data storage circuit may be configured to sample the data signal using the local clock signal during a first operating mode, and to sample the data signal using the pulse signal during a second operating mode.

Abstract: Systems, methods, and devices are provided for calibrating and correcting a clock duty cycle. An integrated circuit may include a clock tree that provides a clock signal and a circuit that is sensitive to clock duty cycle that receives the clock signal at a lower level of the clock tree. A first duty cycle correction circuit may adjust a clock duty cycle of the clock signal to a first target duty cycle at a higher level of the clock tree. A second duty cycle correction circuit may adjust a clock duty cycle of the clock signal to a second target duty cycle at the lower level of the clock tree.

Abstract: A semiconductor device includes a ROM, a differential sense amplifier and a multiplexer logic circuit. The ROM has memory cells in rows along word lines and columns along bit lines, and a reference column having reference transistors along a reference bit line. The multiplexer logic circuit couples a selected bit line to a first differential amplifier input and couples the reference bit line to the second differential amplifier input and controls a reference current of the reference bit line to be between a first bit line current of a programmed memory cell and a second bit line current of an unprogrammed memory cell.

Abstract: An apparatus includes a control circuit configured to selectively activate, based on an operating mode signal, either a local clock signal or a pulse signal. The apparatus further includes a data storage circuit that is coupled to a data signal, the local clock signal, and the pulse signal. The data storage circuit may be configured to sample the data signal using the local clock signal during a first operating mode, and to sample the data signal using the pulse signal during a second operating mode.

Abstract: An apparatus includes a control circuit configured to selectively activate, based on an operating mode signal, either a local clock signal or a pulse signal. The apparatus further includes a data storage circuit that is coupled to a data signal, the local clock signal, and the pulse signal. The data storage circuit may be configured to sample the data signal using the local clock signal during a first operating mode, and to sample the data signal using the pulse signal during a second operating mode.

Abstract: Systems, methods, and devices are provided for calibrating and correcting a clock duty cycle. An integrated circuit may include a clock tree that provides a clock signal and a circuit that is sensitive to clock duty cycle that receives the clock signal at a lower level of the clock tree. A first duty cycle correction circuit may adjust a clock duty cycle of the clock signal to a first target duty cycle at a higher level of the clock tree. A second duty cycle correction circuit may adjust a clock duty cycle of the clock signal to a second target duty cycle at the lower level of the clock tree.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed that improve performance while reading memory. The method includes initializing an output of a of a sensing circuit to be a first logic high value, obtaining, from the memory, a first current corresponding to a memory bit stored in the memory, replicating the first current, determining whether the replicated first current is greater than a second current, and in response to determining that the replicated first current is greater than the second current, generating a second logic high value at the output of the sensing circuit.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to improve performance while reading a one-time programmable memory. An example apparatus includes: a voltage boost circuit including a first output, a second output, a first input configured to be coupled to a controller, a second input coupled to a first output of a decoder, a third input coupled to a second output of the decoder; and a multiplexer including a first input coupled to the first output of the voltage boost circuit, a second input coupled to the second output of the voltage boost circuit, a third input coupled to an array of memory, and an output coupled to a sensing circuit.

Abstract: An apparatus includes a control circuit configured to selectively activate, based on an operating mode signal, either a local clock signal or a pulse signal. The apparatus further includes a data storage circuit that is coupled to a data signal, the local clock signal, and the pulse signal. The data storage circuit may be configured to sample the data signal using the local clock signal during a first operating mode, and to sample the data signal using the pulse signal during a second operating mode.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed that improve performance while reading memory. An example method includes initializing an output of a of a sensing circuit to be a first logic high value, obtaining, from the memory, a first current corresponding to a memory bit stored in the memory, replicating the first current, determining whether the replicated first current is greater than a second current, and in response to determining that the replicated first current is greater than the second current, generating a second logic high value at the output of the sensing circuit.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to improve performance while reading a one-time programmable memory. An example apparatus includes: a voltage boost circuit including a first output, a second output, a first input configured to be coupled to a controller, a second input coupled to a first output of a decoder, a third input coupled to a second output of the decoder; and a multiplexer including a first input coupled to the first output of the voltage boost circuit, a second input coupled to the second output of the voltage boost circuit, a third input coupled to an array of memory, and an output coupled to a sensing circuit.

Abstract: An apparatus includes a control circuit configured to selectively activate, based on an operating mode signal, either a local clock signal or a pulse signal. The apparatus further includes a data storage circuit that is coupled to a data signal, the local clock signal, and the pulse signal. The data storage circuit may be configured to sample the data signal using the local clock signal during a first operating mode, and to sample the data signal using the pulse signal during a second operating mode.

Abstract: An apparatus includes a control circuit configured to selectively activate, based on an operating mode signal, either a local clock signal or a pulse signal. The apparatus further includes a data storage circuit that is coupled to a data signal, the local clock signal, and the pulse signal. The data storage circuit may be configured to sample the data signal using the local clock signal during a first operating mode, and to sample the data signal using the pulse signal during a second operating mode.

Abstract: Presented are end-to-end sales acceleration systems and methods that aid sales people in each phase of the sales process to make sales-related decisions that save time and, ultimately, increase revenue. In various embodiments, this is accomplished by monitoring a sales process and taking advantage of a knowledge database and machine learning to provide sales process recommendations, automation, and analytics throughout the entire sales lifecycle. Task identification and automation allows sales people to carry out the recommended tasks in each step of the sales process with less effort, thereby, improving sales efficiency and performance while minimizing cost.

Abstract: Presented are systems and methods for analyzing a sales process workflow to increasing sales productivity. In embodiments, the system comprises a sales person activity recorder that monitors and records sales-related data according to one or more data categories from one or more data sources; a prospect activity recorder coupled to the sales person activity recorder, the prospect activity recorder monitors and records an interaction associated with a sales prospect; and an analytics processor coupled to the sales person activity recorder, the analytics processor synchronizes sales-related data from one or more data sources, and analyzes, based on at least the interaction, some or all of the data to obtain a result, the analytics processor generates and outputs, based on the analysis, a result that comprises at least one of a progress report, a ranking of prospects, and a sales performance score.

Abstract: Generating a clock signal includes: at a root node of a clock distribution network, receiving a first clock signal; at a first leaf node of the clock distribution network, detecting a reference event and generating a synchronizing signal based on the detection of the reference event; passing the synchronizing signal along a synchronizing signal path from the first leaf node to the root node via one or more clocked storage cells, each storage cell being clocked from a corresponding point within the clock distribution network; at the root node, generating a second clock signal from the first clock signal synchronized to the synchronizing signal received at the root node, and distributing the second clock signal to the leaf nodes of the clock distribution network, the generating of the second clock signal resulting in the second clock signal received at the first leaf node being synchronized to the detected reference event.

Abstract: Generating a clock signal includes: at a root node of a clock distribution network, receiving a first clock signal generated based on a reference clock signal; at a first leaf node, detecting a reference event associated with the reference clock signal and generating a synchronizing signal; passing the synchronizing signal from the first leaf node to the root node; at the root node, generating a second clock signal from the first clock signal synchronized to the synchronizing signal, and distributing the second clock signal to the leaf nodes. Generating the second clock signal includes selecting a repeating pattern of cycles of the first clock signal including fewer than all of the cycles of the first clock signal, and at least every cycle of the first clock signal that is shifted in time by a propagation delay with respect to a rising edge of the reference clock signal.

Abstract: Generating a clock signal includes: at a root node of a clock distribution network, receiving a first clock signal generated based on a reference clock signal; at a first leaf node, detecting a reference event associated with the reference clock signal and generating a synchronizing signal; passing the synchronizing signal from the first leaf node to the root node; at the root node, generating a second clock signal from the first clock signal synchronized to the synchronizing signal, and distributing the second clock signal to the leaf nodes. Generating the second clock signal includes selecting a repeating pattern of cycles of the first clock signal including fewer than all of the cycles of the first clock signal, and at least every cycle of the first clock signal that is shifted in time by a propagation delay with respect to a rising edge of the reference clock signal.

Abstract: Generating a clock signal includes: at a root node of a clock distribution network, receiving a first clock signal; at a first leaf node of the clock distribution network, detecting a reference event and generating a synchronizing signal based on the detection of the reference event; passing the synchronizing signal along a synchronizing signal path from the first leaf node to the root node via one or more clocked storage cells, each storage cell being clocked from a corresponding point within the clock distribution network; at the root node, generating a second clock signal from the first clock signal synchronized to the synchronizing signal received at the root node, and distributing the second clock signal to the leaf nodes of the clock distribution network, the generating of the second clock signal resulting in the second clock signal received at the first leaf node being synchronized to the detected reference event.