Abstract: A processor having binary switches is configured to operate at a predetermined probability value that the logical value of each switch is correct. A supply voltage is coupled to the binary switches. A randomized signal detector is configured to detect a randomized signal, which may be amplified to a predetermined level if the randomized signal is low. A computing element outputs a probabilistic binary bit having a 0 or 1 with a predetermined probability value of being correct in correspondence with the supply voltage and/or an amplification level of a noise signal. Subsequently, an application executed by the processor receives the probabilistic binary bit for one or more additional operations. By operating on the probabilistic binary bits instead of conventional deterministic bits, the processor consumes less energy and completes its execution faster. For battery-powered portable electronic devices, use of processor configured for probabilistic binary bits substantially lengthens battery life.

Abstract: A processor having binary switches is configured to operate at a predetermined probability value that the logical value of each switch is correct. A supply voltage is coupled to the binary switches. A randomized signal detector is configured to detect a randomized signal, which may be amplified to a predetermined level if the randomized signal is low. A computing element outputs a probabilistic binary bit having a 0 or 1 with a predetermined probability value of being correct in correspondence with the supply voltage and/or an amplification level of a noise signal. Subsequently, an application executed by the processor receives the probabilistic binary bit for one or more additional operations. By operating on the probabilistic binary bits instead of conventional deterministic bits, the processor consumes less energy and completes its execution faster. For battery-powered portable electronic devices, use of processor configured for probabilistic binary bits substantially lengthens battery life.

Abstract: A method of sampling marks on a transmission line and adjusting their peak amplitude to compensate for attenuation of signal strength on the line and of "voltage addition" caused by multiple terminals transmitting on the line. For networks meeting the CCITT I-Series Recommendation, two B-channels and a D-channel are transmitted in frames over the line; the B-channel forming the best basis for threshold adaptation, the D-channel the next best basis and the F-bit preceeding each frame used in the absence of either B- or D-channel signals. Accordingly, a B-bit mark sample is taken if possible, otherwise a D-bit mark sample; or if neither is present an F-bit mark sample; the adaptive threshold preferably being set at 55% of the peak value of the sample. The method is readily implemented as a "state machine" and consequently can be constructed from a programmable logic array.