Patents by Inventor Suresh D. Kadakia
Suresh D. Kadakia has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9087834Abstract: A multi-chip electronic package and methods of manufacture are provided. The multi-chip package includes a plurality of chips mounted on a chip carrier. The multi-chip package further includes a lid mounted on the chip carrier using a bonding material or compression seal, and at least one single piston extending from the lid. Each piston covers an entirety of multiple chips of the plurality of chips.Type: GrantFiled: October 28, 2013Date of Patent: July 21, 2015Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Suresh D. Kadakia, Kamal K. Sikka, Hilton T. Toy, Jeffrey A. Zitz
-
Publication number: 20140051211Abstract: A multi-chip electronic package and methods of manufacture are provided. The multi-chip package includes a plurality of chips mounted on a chip carrier. The multi-chip package further includes a lid mounted on the chip carrier using a bonding material or compression seal, and at least one single piston extending from the lid. Each piston covers an entirety of multiple chips of the plurality of chips.Type: ApplicationFiled: October 28, 2013Publication date: February 20, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Suresh D. KADAKIA, Kamal K. SIKKA, Hilton T. TOY, Jeffrey A. ZITZ
-
Patent number: 8587114Abstract: A multi-chip electronic package and methods of manufacture are provided. The multi-chip package includes a plurality of chips mounted on a chip carrier. The multi-chip package further includes a lid mounted on the chip carrier using a bonding material or compression seal, and at least one single piston extending from the lid. Each piston covers an entirety of multiple chips of the plurality of chips.Type: GrantFiled: October 5, 2010Date of Patent: November 19, 2013Assignee: International Business Machines CorporationInventors: Suresh D. Kadakia, Kamal K. Sikka, Hilton T. Toy, Jeffrey A. Zitz
-
Patent number: 8445331Abstract: A multi-chip electronic package and methods of manufacture are provided. The multi-chip package includes a plurality of chips mounted on a chip carrier. The multi-chip package further includes a lid mounted on the chip carrier using a bonding material or compression seal, and at least one single piston extending from the lid. Each piston covers an entirety of multiple chips of the plurality of chips.Type: GrantFiled: March 29, 2012Date of Patent: May 21, 2013Assignee: International Business Machines CorporationInventors: Suresh D. Kadakia, Kamal K. Sikka, Hilton T. Toy, Jeffrey A. Zitz
-
Publication number: 20120196408Abstract: A multi-chip electronic package and methods of manufacture are provided. The multi-chip package includes a plurality of chips mounted on a chip carrier. The multi-chip package further includes a lid mounted on the chip carrier using a bonding material or compression seal, and at least one single piston extending from the lid. Each piston covers an entirety of multiple chips of the plurality of chips.Type: ApplicationFiled: March 29, 2012Publication date: August 2, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Suresh D. KADAKIA, Kamal K. SIKKA, Hilton T. TOY, Jeffrey A. ZITZ
-
Publication number: 20120080784Abstract: A multi-chip electronic package and methods of manufacture are provided. The multi-chip package includes a plurality of chips mounted on a chip carrier. The multi-chip package further includes a lid mounted on the chip carrier using a bonding material or compression seal, and at least one single piston extending from the lid. Each piston covers an entirety of multiple chips of the plurality of chips.Type: ApplicationFiled: October 5, 2010Publication date: April 5, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: SURESH D. KADAKIA, Kamal K. Sikka, Hilton T. Toy, Jeffrey A. Zitz
-
Patent number: 7806341Abstract: A tamper resistant, integrated circuit (IC) module includes a ceramic-based chip carrier; one or more integrated circuit chips attached to a top surface of the chip carrier; a ceramic-based cap structure attached to the top surface of the chip carrier, and covering the one or more integrated circuit chips; and a conductive grid structure embedded within the chip carrier and the cap structure, the conductive grid structure having a plurality of meandering lines disposed in an x-direction, a y-direction, and a z-direction; wherein the conductive grid structure is configured so as to detect an attempt to penetrate the IC module.Type: GrantFiled: January 5, 2009Date of Patent: October 5, 2010Assignee: International Business Machines CorporationInventors: Mukta G. Farooq, Benjamin V. Fasano, Jason L. Frankel, Harvey C. Hamel, Suresh D. Kadakia, David C. Long, Frank L. Pompeo, Sudipta K. Ray
-
Publication number: 20090145973Abstract: A tamper resistant, integrated circuit (IC) module includes a ceramic-based chip carrier; one or more integrated circuit chips attached to a top surface of the chip carrier; a ceramic-based cap structure attached to the top surface of the chip carrier, and covering the one or more integrated circuit chips; and a conductive grid structure embedded within the chip carrier and the cap structure, the conductive grid structure having a plurality of meandering lines disposed in an x-direction, a y-direction, and a z-direction; wherein the conductive grid structure is configured so as to detect an attempt to penetrate the IC module.Type: ApplicationFiled: January 5, 2009Publication date: June 11, 2009Applicant: International Business Machines CorporationInventors: Mukta G. Farooq, Benjamin V. Fasano, Jason L. Frankel, Harvey C. Hamel, Suresh D. Kadakia, David C. Long, Frank L. Pompeo, Sudipta K. Ray
-
Patent number: 7472836Abstract: A tamper resistant, integrated circuit (IC) module includes a ceramic-based chip carrier, one or more integrated circuit chips attached to the chip carrier, and a cap structure attached to the chip carrier, covering the one or more integrated circuit chips. A conductive grid structure is formed in the chip carrier and cap structure, the conductive structure having a plurality of meandering lines disposed in an x-direction, a y-direction, and a z-direction. The conductive grid structure is configured so as to detect an attempt to penetrate the IC module.Type: GrantFiled: June 26, 2007Date of Patent: January 6, 2009Assignee: International Business Machines CorporationInventors: Mukta G. Farooq, Benjamin V. Fasano, Jason L. Frankel, Harvey C. Hamel, Suresh D. Kadakia, David C. Long, Frank L. Pompeo, Sudipta K. Ray
-
Patent number: 7281667Abstract: A tamper resistant, integrated circuit (IC) module includes a ceramic-based chip carrier, one or more integrated circuit chips attached to the chip carrier, and a cap structure attached to the chip carrier, covering the one or more integrated circuit chips. A conductive grid structure is formed in the chip carrier and cap structure, the conductive structure having a plurality of meandering lines disposed in an x-direction, a y-direction, and a z-direction. The conductive grid structure is configured so as to detect an attempt to penetrate the IC module.Type: GrantFiled: April 14, 2005Date of Patent: October 16, 2007Assignee: International Business Machines CorporationInventors: Mukta G. Farooq, Benjamin V. Fasano, Jason L. Frankel, Harvey C. Hamel, Suresh D Kadakia, David C. Long, Frank L. Pompeo, Sudipta K. Ray
-
Patent number: 6179951Abstract: The present invention relates generally to a new apparatus and method for forming non-planar surfaces in substrates. More particularly, the invention encompasses an apparatus and a method for fabricating non-planar surfaces in semiconductor substrates wherein at least one zero compression set pad, such as a closed cell porous pad in combination with at least one elastic pad is placed over the non-planar surface prior to lamination and is caused to conform to the contour of the non-planar surface, thus preventing collapse of, or damage to, the non-planar features, such as, shelves or corners during the lamination process. After the lamination process, the zero compression set pad are conveniently removed from the non-planar surface area without causing any damage to the non-planar surface features, such as, shelves or corners or having any paste pull-outs. These zero compression set pads can be reused multiple number of times to form these MLC cavity substrates or similar other structures or features.Type: GrantFiled: March 5, 1999Date of Patent: January 30, 2001Assignee: International Business Machines CorporationInventors: Govindarajan Natarajan, John U. Knickerbocker, Suresh D. Kadakia, Abubaker S. Shagan
-
Patent number: 5831810Abstract: An electronic component package comprising a substrate having at least one die-receiving cavity formed therein, the cavity being defined by a die-receiving surface and an inner sidewall having a terraced contour, the substrate having an exterior surface bordering the cavity perimeter, the inner sidewall extending between the die-receiving surface and the substrate exterior surface, and at least one capacitor positioned completely within the cavity and mounted to the terraced contour of the inner sidewall.Type: GrantFiled: August 21, 1996Date of Patent: November 3, 1998Assignee: International Business Machines CorporationInventors: Kenneth A. Bird, Peter J. Brofman, Francis F. Cappo, Jr., Jason L. Frankel, Suresh D. Kadakia, Sarah Huffsmith Knickerbocker, Scott A. Sikorski
-
Patent number: 5243140Abstract: A direct distribution wiring system is provided which facilitates the effecting of repair or engineering change in a Multi-chip module (MCM) while eliminating the need for redistribution and/or buried connections between IC attachment pads and engineering change pads, thus eliminating the need for patterned conductor layers corresponding to such functions. The operation of the MCM is improved by the wiring system allowing the reduction of lumped capacitances by disconnection of defective conductors, accomplished by providing severable connectors in a direct distribution structure, as well as the elimination of redistribution wiring layers and increased IC density on the MCM. Full potential fault coverage as well as full discretion in reversible engineering changes is provided by forming all elements of the wiring system on the surface of the device.Type: GrantFiled: October 4, 1991Date of Patent: September 7, 1993Assignee: International Business Machines CorporationInventors: Harsaran S. Bhatia, Mario J. Interrante, Suresh D. Kadakia, Shashi D. Malaviya, Mark H. McLeod, Sudipta K. Ray, Herbert I. Stoller