Patents by Inventor Suresh E. Warrier
Suresh E. Warrier has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11010199Abstract: An operating system interface, responsive to detecting a non-privileged thread request with a scheduling attribute set to a critical setting to request access to at least one privileged core, selectively schedules the non-privileged thread request into a privileged core queue associated with the at least one privileged core only when a resource availability of the at least one privileged class core meets a threshold level of availability, the at least one privileged core providing a higher throughput than at least one regular core. The operating system interface, responsive to detecting a privileged thread request with the scheduling attribute set to the critical setting, automatically scheduling the privileged thread request into the privileged core queue.Type: GrantFiled: December 1, 2017Date of Patent: May 18, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Bruce Mealey, Suresh E. Warrier
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Patent number: 10896065Abstract: An operating system interface, responsive to detecting a non-privileged thread request with a scheduling attribute set to a critical setting to request access to at least one privileged core, selectively schedules the non-privileged thread request into a privileged core queue associated with the at least one privileged core only when a resource availability of the at least one privileged class core meets a threshold level of availability, the at least one privileged core providing a higher throughput than at least one regular core. The operating system interface, responsive to detecting a privileged thread request with the scheduling attribute set to the critical setting, automatically scheduling the privileged thread request into the privileged core queue.Type: GrantFiled: December 1, 2017Date of Patent: January 19, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Bruce Mealey, Suresh E. Warrier
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Publication number: 20180101409Abstract: An operating system interface, responsive to detecting a non-privileged thread request with a scheduling attribute set to a critical setting to request access to at least one privileged core, selectively schedules the non-privileged thread request into a privileged core queue associated with the at least one privileged core only when a resource availability of the at least one privileged class core meets a threshold level of availability, the at least one privileged core providing a higher throughput than at least one regular core. The operating system interface, responsive to detecting a privileged thread request with the scheduling attribute set to the critical setting, automatically scheduling the privileged thread request into the privileged core queue.Type: ApplicationFiled: December 1, 2017Publication date: April 12, 2018Inventors: BRUCE MEALEY, SURESH E. WARRIER
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Publication number: 20180081732Abstract: An operating system interface, responsive to detecting a non-privileged thread request with a scheduling attribute set to a critical setting to request access to at least one privileged core, selectively schedules the non-privileged thread request into a privileged core queue associated with the at least one privileged core only when a resource availability of the at least one privileged class core meets a threshold level of availability, the at least one privileged core providing a higher throughput than at least one regular core. The operating system interface, responsive to detecting a privileged thread request with the scheduling attribute set to the critical setting, automatically scheduling the privileged thread request into the privileged core queue.Type: ApplicationFiled: December 1, 2017Publication date: March 22, 2018Inventors: BRUCE MEALEY, SURESH E. WARRIER
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Patent number: 9904580Abstract: An operating system interface, responsive to detecting a non-privileged thread request with a scheduling attribute set to a critical setting to request access to at least one privileged core, selectively schedules the non-privileged thread request into a privileged core queue associated with the at least one privileged core only when a resource availability of the at least one privileged class core meets a threshold level of availability, the at least one privileged core providing a higher throughput than at least one regular core. The operating system interface, responsive to detecting a privileged thread request with the scheduling attribute set to the critical setting, automatically scheduling the privileged thread request into the privileged core queue.Type: GrantFiled: May 29, 2015Date of Patent: February 27, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Bruce Mealey, Suresh E. Warrier
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Patent number: 9891956Abstract: An operating system interface, responsive to detecting a non-privileged thread request with a scheduling attribute set to a critical setting to request access to at least one privileged core, selectively schedules the non-privileged thread request into a privileged core queue associated with the at least one privileged core only when a resource availability of the at least one privileged class core meets a threshold level of availability, the at least one privileged core providing a higher throughput than at least one regular core. The operating system interface, responsive to detecting a privileged thread request with the scheduling attribute set to the critical setting, automatically scheduling the privileged thread request into the privileged core queue.Type: GrantFiled: August 14, 2015Date of Patent: February 13, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Bruce Mealey, Suresh E. Warrier
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Patent number: 9817696Abstract: A method is provided for prioritized hardware thread scheduling. The method includes, responsive to identifying a latency sensitive workload, enabling, by an operating system, one or more hardware threads to meet dispatch latency demands for the latency sensitive workload. The method further includes responsive to detecting an absence of the latency sensitive workload, de-committing, by the operating system, the one or more hardware threads.Type: GrantFiled: February 24, 2016Date of Patent: November 14, 2017Assignee: International Business Machines CoroporationInventors: Bruce Mealey, Suresh E. Warrier
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Patent number: 9798582Abstract: A computer program product is provided for prioritized hardware thread scheduling. The computer program product includes a non-transitory computer readable storage medium having program instructions embodied therewith. The program instructions are executable by a computer to cause the computer to perform a method. The method includes, responsive to identifying a latency sensitive workload, enabling, by an operating system, one or more hardware threads to meet dispatch latency demands for the latency sensitive workload. The method further includes responsive to detecting an absence of the latency sensitive workload, de-committing, by the operating system, the one or more hardware threads.Type: GrantFiled: October 22, 2015Date of Patent: October 24, 2017Assignee: International Business Machines CorporationInventors: Bruce Mealey, Suresh E. Warrier
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Publication number: 20170116030Abstract: A computer program product is provided for prioritized hardware thread scheduling. The computer program product includes a non-transitory computer readable storage medium having program instructions embodied therewith. The program instructions are executable by a computer to cause the computer to perform a method. The method includes, responsive to identifying a latency sensitive workload, enabling, by an operating system, one or more hardware threads to meet dispatch latency demands for the latency sensitive workload. The method further includes responsive to detecting an absence of the latency sensitive workload, de-committing, by the operating system, the one or more hardware threads.Type: ApplicationFiled: October 22, 2015Publication date: April 27, 2017Inventors: BRUCE MEALEY, SURESH E. WARRIER
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Publication number: 20170116039Abstract: A method is provided for prioritized hardware thread scheduling. The method includes, responsive to identifying a latency sensitive workload, enabling, by an operating system, one or more hardware threads to meet dispatch latency demands for the latency sensitive workload. The method further includes responsive to detecting an absence of the latency sensitive workload, de-committing, by the operating system, the one or more hardware threads.Type: ApplicationFiled: February 24, 2016Publication date: April 27, 2017Inventors: BRUCE MEALEY, SURESH E. WARRIER
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Publication number: 20160350159Abstract: An operating system interface, responsive to detecting a non-privileged thread request with a scheduling attribute set to a critical setting to request access to at least one privileged core, selectively schedules the non-privileged thread request into a privileged core queue associated with the at least one privileged core only when a resource availability of the at least one privileged class core meets a threshold level of availability, the at least one privileged core providing a higher throughput than at least one regular core. The operating system interface, responsive to detecting a privileged thread request with the scheduling attribute set to the critical setting, automatically scheduling the privileged thread request into the privileged core queue.Type: ApplicationFiled: August 14, 2015Publication date: December 1, 2016Inventors: BRUCE MEALEY, SURESH E. WARRIER
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Publication number: 20160350158Abstract: An operating system interface, responsive to detecting a non-privileged thread request with a scheduling attribute set to a critical setting to request access to at least one privileged core, selectively schedules the non-privileged thread request into a privileged core queue associated with the at least one privileged core only when a resource availability of the at least one privileged class core meets a threshold level of availability, the at least one privileged core providing a higher throughput than at least one regular core. The operating system interface, responsive to detecting a privileged thread request with the scheduling attribute set to the critical setting, automatically scheduling the privileged thread request into the privileged core queue.Type: ApplicationFiled: May 29, 2015Publication date: December 1, 2016Inventors: BRUCE MEALEY, SURESH E. WARRIER
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Patent number: 9229716Abstract: According to one aspect of the present disclosure, a method and technique for task priority boost management is disclosed. The method includes: responsive to a thread executing in user mode an instruction to boost a priority of the thread, accessing a boost register, the boost register accessible in kernel mode; determining a value of the boost register; and responsive to determining that the boost register holds a non-zero value, boosting the priority of the thread.Type: GrantFiled: December 12, 2011Date of Patent: January 5, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Christopher Francois, Giles R. Frazier, Bruce G. Mealey, Suresh E. Warrier
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Patent number: 8874805Abstract: A mechanism is provided for offloading an input/output (I/O) completion operation. Responsive to a second processor identifying that a flag has been set by a first processor requesting assistance in completing an I/O operation, the second processor copies an I/O response from a first I/O response data structure associated with the first processor to a second I/O response data structure associated with the second processor. The second processor deletes the I/O response from the first I/O response data structure, clears the flag, and processes the I/O operation by addressing the I/O response in the second I/O response data structure. Responsive to completing the I/O operation, the second processor deletes the I/O response from the second I/O response data structure.Type: GrantFiled: November 19, 2012Date of Patent: October 28, 2014Assignee: International Business Machines CorporationInventors: Bruce G. Mealey, Greg R. Mewhinney, Mysore S. Srinivas, Suresh E. Warrier
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Patent number: 8843673Abstract: A mechanism is provided for offloading an input/output (I/O) completion operation. Responsive to a second processor identifying that a flag has been set by a first processor requesting assistance in completing an I/O operation, the second processor copies an I/O response from a first I/O response data structure associated with the first processor to a second I/O response data structure associated with the second processor. The second processor deletes the I/O response from the first I/O response data structure, clears the flag, and processes the I/O operation by addressing the I/O response in the second I/O response data structure. Responsive to completing the I/O operation, the second processor deletes the I/O response from the second I/O response data structure.Type: GrantFiled: February 20, 2013Date of Patent: September 23, 2014Assignee: International Business Machines CorporationInventors: Bruce G. Mealey, Greg R. Mewhinney, Mysore S. Srinivas, Suresh E. Warrier
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Publication number: 20140143465Abstract: A mechanism is provided for offloading an input/output (I/O) completion operation. Responsive to a second processor identifying that a flag has been set by a first processor requesting assistance in completing an I/O operation, the second processor copies an I/O response from a first I/O response data structure associated with the first processor to a second I/O response data structure associated with the second processor. The second processor deletes the I/O response from the first I/O response data structure, clears the flag, and processes the I/O operation by addressing the I/O response in the second I/O response data structure. Responsive to completing the I/O operation, the second processor deletes the I/O response from the second I/O response data structure.Type: ApplicationFiled: February 20, 2013Publication date: May 22, 2014Applicant: International Business Machines CorporationInventors: Bruce G. Mealey, Greg R. Mewhinney, Mysore S. Srinivas, Suresh E. Warrier
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Publication number: 20140143458Abstract: A mechanism is provided for offloading an input/output (I/O) completion operation. Responsive to a second processor identifying that a flag has been set by a first processor requesting assistance in completing an I/O operation, the second processor copies an I/O response from a first I/O response data structure associated with the first processor to a second I/O response data structure associated with the second processor. The second processor deletes the I/O response from the first I/O response data structure, clears the flag, and processes the I/O operation by addressing the I/O response in the second I/O response data structure. Responsive to completing the I/O operation, the second processor deletes the I/O response from the second I/O response data structure.Type: ApplicationFiled: November 19, 2012Publication date: May 22, 2014Applicant: International Business Machines CorporationInventors: Bruce G. Mealey, Greg R. Mewhinney, Mysore S. Srinivas, Suresh E. Warrier
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Publication number: 20130152098Abstract: According to one aspect of the present disclosure, a method and technique for task priority boost management is disclosed. The method includes: responsive to a thread executing in user mode an instruction to boost a priority of the thread, accessing a boost register, the boost register accessible in kernel mode; determining a value of the boost register; and responsive to determining that the boost register holds a non-zero value, boosting the priority of the thread.Type: ApplicationFiled: December 12, 2011Publication date: June 13, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Christopher Francois, Giles R. Frazier, Bruce G. Mealey, Suresh E. Warrier
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Patent number: 8327368Abstract: A kernel of a SMT enabled processor system facilitates construction of an exclusive set of processors to simulate an ST mode for handling the tasks of the ST workload, wherein the ST workload runs more efficiently on single threaded processors. The kernel schedules the ST workload on the exclusive set of processors by selecting one hardware thread per processor within said exclusive set of processors to handle a separate one of the tasks of the ST workload, while requiring the remaining hardware threads per processor within the exclusive set to idle. As a result, the ST workload is executed on the SMT enabled processor system as if the exclusive set of processors run in ST mode, but without actually deactivating the remaining idle hardware threads per processor within the exclusive set of processors.Type: GrantFiled: November 25, 2011Date of Patent: December 4, 2012Assignee: International Business Machines CorporationInventors: Michael G. Mall, James B. Moody, Suresh E. Warrier
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Publication number: 20120084778Abstract: A kernel of a SMT enabled processor system facilitates construction of an exclusive set of processors to simulate an ST mode for handling the tasks of the ST workload, wherein the ST workload runs more efficiently on single threaded processors. The kernel schedules the ST workload on the exclusive set of processors by selecting one hardware thread per processor within said exclusive set of processors to handle a separate one of the tasks of the ST workload, while requiring the remaining hardware threads per processor within the exclusive set to idle. As a result, the ST workload is executed on the SMT enabled processor system as if the exclusive set of processors run in ST mode, but without actually deactivating the remaining idle hardware threads per processor within the exclusive set of processors.Type: ApplicationFiled: November 25, 2011Publication date: April 5, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: MICHAEL G. MALL, JAMES B. MOODY, SURESH E. WARRIER