Patents by Inventor Suresh E. Warrier

Suresh E. Warrier has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11010199
    Abstract: An operating system interface, responsive to detecting a non-privileged thread request with a scheduling attribute set to a critical setting to request access to at least one privileged core, selectively schedules the non-privileged thread request into a privileged core queue associated with the at least one privileged core only when a resource availability of the at least one privileged class core meets a threshold level of availability, the at least one privileged core providing a higher throughput than at least one regular core. The operating system interface, responsive to detecting a privileged thread request with the scheduling attribute set to the critical setting, automatically scheduling the privileged thread request into the privileged core queue.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: May 18, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bruce Mealey, Suresh E. Warrier
  • Patent number: 10896065
    Abstract: An operating system interface, responsive to detecting a non-privileged thread request with a scheduling attribute set to a critical setting to request access to at least one privileged core, selectively schedules the non-privileged thread request into a privileged core queue associated with the at least one privileged core only when a resource availability of the at least one privileged class core meets a threshold level of availability, the at least one privileged core providing a higher throughput than at least one regular core. The operating system interface, responsive to detecting a privileged thread request with the scheduling attribute set to the critical setting, automatically scheduling the privileged thread request into the privileged core queue.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: January 19, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bruce Mealey, Suresh E. Warrier
  • Publication number: 20180101409
    Abstract: An operating system interface, responsive to detecting a non-privileged thread request with a scheduling attribute set to a critical setting to request access to at least one privileged core, selectively schedules the non-privileged thread request into a privileged core queue associated with the at least one privileged core only when a resource availability of the at least one privileged class core meets a threshold level of availability, the at least one privileged core providing a higher throughput than at least one regular core. The operating system interface, responsive to detecting a privileged thread request with the scheduling attribute set to the critical setting, automatically scheduling the privileged thread request into the privileged core queue.
    Type: Application
    Filed: December 1, 2017
    Publication date: April 12, 2018
    Inventors: BRUCE MEALEY, SURESH E. WARRIER
  • Publication number: 20180081732
    Abstract: An operating system interface, responsive to detecting a non-privileged thread request with a scheduling attribute set to a critical setting to request access to at least one privileged core, selectively schedules the non-privileged thread request into a privileged core queue associated with the at least one privileged core only when a resource availability of the at least one privileged class core meets a threshold level of availability, the at least one privileged core providing a higher throughput than at least one regular core. The operating system interface, responsive to detecting a privileged thread request with the scheduling attribute set to the critical setting, automatically scheduling the privileged thread request into the privileged core queue.
    Type: Application
    Filed: December 1, 2017
    Publication date: March 22, 2018
    Inventors: BRUCE MEALEY, SURESH E. WARRIER
  • Patent number: 9904580
    Abstract: An operating system interface, responsive to detecting a non-privileged thread request with a scheduling attribute set to a critical setting to request access to at least one privileged core, selectively schedules the non-privileged thread request into a privileged core queue associated with the at least one privileged core only when a resource availability of the at least one privileged class core meets a threshold level of availability, the at least one privileged core providing a higher throughput than at least one regular core. The operating system interface, responsive to detecting a privileged thread request with the scheduling attribute set to the critical setting, automatically scheduling the privileged thread request into the privileged core queue.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: February 27, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bruce Mealey, Suresh E. Warrier
  • Patent number: 9891956
    Abstract: An operating system interface, responsive to detecting a non-privileged thread request with a scheduling attribute set to a critical setting to request access to at least one privileged core, selectively schedules the non-privileged thread request into a privileged core queue associated with the at least one privileged core only when a resource availability of the at least one privileged class core meets a threshold level of availability, the at least one privileged core providing a higher throughput than at least one regular core. The operating system interface, responsive to detecting a privileged thread request with the scheduling attribute set to the critical setting, automatically scheduling the privileged thread request into the privileged core queue.
    Type: Grant
    Filed: August 14, 2015
    Date of Patent: February 13, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bruce Mealey, Suresh E. Warrier
  • Patent number: 9817696
    Abstract: A method is provided for prioritized hardware thread scheduling. The method includes, responsive to identifying a latency sensitive workload, enabling, by an operating system, one or more hardware threads to meet dispatch latency demands for the latency sensitive workload. The method further includes responsive to detecting an absence of the latency sensitive workload, de-committing, by the operating system, the one or more hardware threads.
    Type: Grant
    Filed: February 24, 2016
    Date of Patent: November 14, 2017
    Assignee: International Business Machines Coroporation
    Inventors: Bruce Mealey, Suresh E. Warrier
  • Patent number: 9798582
    Abstract: A computer program product is provided for prioritized hardware thread scheduling. The computer program product includes a non-transitory computer readable storage medium having program instructions embodied therewith. The program instructions are executable by a computer to cause the computer to perform a method. The method includes, responsive to identifying a latency sensitive workload, enabling, by an operating system, one or more hardware threads to meet dispatch latency demands for the latency sensitive workload. The method further includes responsive to detecting an absence of the latency sensitive workload, de-committing, by the operating system, the one or more hardware threads.
    Type: Grant
    Filed: October 22, 2015
    Date of Patent: October 24, 2017
    Assignee: International Business Machines Corporation
    Inventors: Bruce Mealey, Suresh E. Warrier
  • Publication number: 20170116030
    Abstract: A computer program product is provided for prioritized hardware thread scheduling. The computer program product includes a non-transitory computer readable storage medium having program instructions embodied therewith. The program instructions are executable by a computer to cause the computer to perform a method. The method includes, responsive to identifying a latency sensitive workload, enabling, by an operating system, one or more hardware threads to meet dispatch latency demands for the latency sensitive workload. The method further includes responsive to detecting an absence of the latency sensitive workload, de-committing, by the operating system, the one or more hardware threads.
    Type: Application
    Filed: October 22, 2015
    Publication date: April 27, 2017
    Inventors: BRUCE MEALEY, SURESH E. WARRIER
  • Publication number: 20170116039
    Abstract: A method is provided for prioritized hardware thread scheduling. The method includes, responsive to identifying a latency sensitive workload, enabling, by an operating system, one or more hardware threads to meet dispatch latency demands for the latency sensitive workload. The method further includes responsive to detecting an absence of the latency sensitive workload, de-committing, by the operating system, the one or more hardware threads.
    Type: Application
    Filed: February 24, 2016
    Publication date: April 27, 2017
    Inventors: BRUCE MEALEY, SURESH E. WARRIER
  • Publication number: 20160350159
    Abstract: An operating system interface, responsive to detecting a non-privileged thread request with a scheduling attribute set to a critical setting to request access to at least one privileged core, selectively schedules the non-privileged thread request into a privileged core queue associated with the at least one privileged core only when a resource availability of the at least one privileged class core meets a threshold level of availability, the at least one privileged core providing a higher throughput than at least one regular core. The operating system interface, responsive to detecting a privileged thread request with the scheduling attribute set to the critical setting, automatically scheduling the privileged thread request into the privileged core queue.
    Type: Application
    Filed: August 14, 2015
    Publication date: December 1, 2016
    Inventors: BRUCE MEALEY, SURESH E. WARRIER
  • Publication number: 20160350158
    Abstract: An operating system interface, responsive to detecting a non-privileged thread request with a scheduling attribute set to a critical setting to request access to at least one privileged core, selectively schedules the non-privileged thread request into a privileged core queue associated with the at least one privileged core only when a resource availability of the at least one privileged class core meets a threshold level of availability, the at least one privileged core providing a higher throughput than at least one regular core. The operating system interface, responsive to detecting a privileged thread request with the scheduling attribute set to the critical setting, automatically scheduling the privileged thread request into the privileged core queue.
    Type: Application
    Filed: May 29, 2015
    Publication date: December 1, 2016
    Inventors: BRUCE MEALEY, SURESH E. WARRIER
  • Patent number: 9229716
    Abstract: According to one aspect of the present disclosure, a method and technique for task priority boost management is disclosed. The method includes: responsive to a thread executing in user mode an instruction to boost a priority of the thread, accessing a boost register, the boost register accessible in kernel mode; determining a value of the boost register; and responsive to determining that the boost register holds a non-zero value, boosting the priority of the thread.
    Type: Grant
    Filed: December 12, 2011
    Date of Patent: January 5, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Christopher Francois, Giles R. Frazier, Bruce G. Mealey, Suresh E. Warrier
  • Patent number: 8874805
    Abstract: A mechanism is provided for offloading an input/output (I/O) completion operation. Responsive to a second processor identifying that a flag has been set by a first processor requesting assistance in completing an I/O operation, the second processor copies an I/O response from a first I/O response data structure associated with the first processor to a second I/O response data structure associated with the second processor. The second processor deletes the I/O response from the first I/O response data structure, clears the flag, and processes the I/O operation by addressing the I/O response in the second I/O response data structure. Responsive to completing the I/O operation, the second processor deletes the I/O response from the second I/O response data structure.
    Type: Grant
    Filed: November 19, 2012
    Date of Patent: October 28, 2014
    Assignee: International Business Machines Corporation
    Inventors: Bruce G. Mealey, Greg R. Mewhinney, Mysore S. Srinivas, Suresh E. Warrier
  • Patent number: 8843673
    Abstract: A mechanism is provided for offloading an input/output (I/O) completion operation. Responsive to a second processor identifying that a flag has been set by a first processor requesting assistance in completing an I/O operation, the second processor copies an I/O response from a first I/O response data structure associated with the first processor to a second I/O response data structure associated with the second processor. The second processor deletes the I/O response from the first I/O response data structure, clears the flag, and processes the I/O operation by addressing the I/O response in the second I/O response data structure. Responsive to completing the I/O operation, the second processor deletes the I/O response from the second I/O response data structure.
    Type: Grant
    Filed: February 20, 2013
    Date of Patent: September 23, 2014
    Assignee: International Business Machines Corporation
    Inventors: Bruce G. Mealey, Greg R. Mewhinney, Mysore S. Srinivas, Suresh E. Warrier
  • Publication number: 20140143465
    Abstract: A mechanism is provided for offloading an input/output (I/O) completion operation. Responsive to a second processor identifying that a flag has been set by a first processor requesting assistance in completing an I/O operation, the second processor copies an I/O response from a first I/O response data structure associated with the first processor to a second I/O response data structure associated with the second processor. The second processor deletes the I/O response from the first I/O response data structure, clears the flag, and processes the I/O operation by addressing the I/O response in the second I/O response data structure. Responsive to completing the I/O operation, the second processor deletes the I/O response from the second I/O response data structure.
    Type: Application
    Filed: February 20, 2013
    Publication date: May 22, 2014
    Applicant: International Business Machines Corporation
    Inventors: Bruce G. Mealey, Greg R. Mewhinney, Mysore S. Srinivas, Suresh E. Warrier
  • Publication number: 20140143458
    Abstract: A mechanism is provided for offloading an input/output (I/O) completion operation. Responsive to a second processor identifying that a flag has been set by a first processor requesting assistance in completing an I/O operation, the second processor copies an I/O response from a first I/O response data structure associated with the first processor to a second I/O response data structure associated with the second processor. The second processor deletes the I/O response from the first I/O response data structure, clears the flag, and processes the I/O operation by addressing the I/O response in the second I/O response data structure. Responsive to completing the I/O operation, the second processor deletes the I/O response from the second I/O response data structure.
    Type: Application
    Filed: November 19, 2012
    Publication date: May 22, 2014
    Applicant: International Business Machines Corporation
    Inventors: Bruce G. Mealey, Greg R. Mewhinney, Mysore S. Srinivas, Suresh E. Warrier
  • Publication number: 20130152098
    Abstract: According to one aspect of the present disclosure, a method and technique for task priority boost management is disclosed. The method includes: responsive to a thread executing in user mode an instruction to boost a priority of the thread, accessing a boost register, the boost register accessible in kernel mode; determining a value of the boost register; and responsive to determining that the boost register holds a non-zero value, boosting the priority of the thread.
    Type: Application
    Filed: December 12, 2011
    Publication date: June 13, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Christopher Francois, Giles R. Frazier, Bruce G. Mealey, Suresh E. Warrier
  • Patent number: 8327368
    Abstract: A kernel of a SMT enabled processor system facilitates construction of an exclusive set of processors to simulate an ST mode for handling the tasks of the ST workload, wherein the ST workload runs more efficiently on single threaded processors. The kernel schedules the ST workload on the exclusive set of processors by selecting one hardware thread per processor within said exclusive set of processors to handle a separate one of the tasks of the ST workload, while requiring the remaining hardware threads per processor within the exclusive set to idle. As a result, the ST workload is executed on the SMT enabled processor system as if the exclusive set of processors run in ST mode, but without actually deactivating the remaining idle hardware threads per processor within the exclusive set of processors.
    Type: Grant
    Filed: November 25, 2011
    Date of Patent: December 4, 2012
    Assignee: International Business Machines Corporation
    Inventors: Michael G. Mall, James B. Moody, Suresh E. Warrier
  • Publication number: 20120084778
    Abstract: A kernel of a SMT enabled processor system facilitates construction of an exclusive set of processors to simulate an ST mode for handling the tasks of the ST workload, wherein the ST workload runs more efficiently on single threaded processors. The kernel schedules the ST workload on the exclusive set of processors by selecting one hardware thread per processor within said exclusive set of processors to handle a separate one of the tasks of the ST workload, while requiring the remaining hardware threads per processor within the exclusive set to idle. As a result, the ST workload is executed on the SMT enabled processor system as if the exclusive set of processors run in ST mode, but without actually deactivating the remaining idle hardware threads per processor within the exclusive set of processors.
    Type: Application
    Filed: November 25, 2011
    Publication date: April 5, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: MICHAEL G. MALL, JAMES B. MOODY, SURESH E. WARRIER