Patents by Inventor Suresh K. B. Dholakia

Suresh K. B. Dholakia has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Automated method of inserting pipeline stages in a data path element to achieve a specified operating frequency
    Patent number: 5212782
    Abstract: According to a technique for determining delays through multi-stage datapath elements, estimates of the delays through each stage of the datapath element are computed in accordance with an the equation such as:D.sub.s =D.sub.b N.sub.b +Cwhere D.sub.s is the estimated stage delay, D.sub.b is a delay associated with communication between bits in the stage, N.sub.b is the number of bits in the datapath element, and C is a constant. The estimated stage delays are used to determine positions of pipelining stages in the datapath element.
    Type: Grant
    Filed: April 1, 1991
    Date of Patent: May 18, 1993
    Assignee: VLSI Technology, Inc.
    Inventors: Creigton S. Asato, Suresh K. B. Dholakia, Christoph Ditzen