Abstract: A system and method for injecting hardware errors into a microprocessor system is described. In one embodiment, a software interface between system software and system firmware is established. Software test and debug for software error handlers may thus be supported. The software interface may support both a query mode call and a seed mode call. When a query mode call is issued, it may request whether or not the system firmware and hardware support the injection of a specified kind of error. A return from this call may be used to make a list of supported errors for injection. When a seed mode call is issued, the corresponding error may be injected into the hardware.

Abstract: A symmetric multiprocessing system with a unified environment and distributed system functions provides unified address space for all functional units in the system while distributing the execution of various system functions over the functional units of the system whereby each functional unit assumes responsibility for its own aspects of these operations. In addition, the system provides improved system bus operation for transfer of data from memory.

Abstract: The present invention provides a method and apparatus for maintaining application integrity in a hot, disconnected network environment. The present invention provides a system having a computer subsystem with a processor executing application programs in an operating system environment. The system also includes a network and a connection to connect the network to the computer system. A notification mechanism detects when the network resources are no longer connected and permits continued use of the computer subsystem while it remains disconnected from the network.

Abstract: Timing calculator means in a computer system are used to adaptively generate an appropriate access signal, to one of a plurality of memory types, based on first and second timing control values, wherein the first timing control value represents information specific to and limited to the start of a memory operation and wherein the second timing control value represents information representing other timing events. That is, the state machine of the present invention requires a distinct starting control value, separate from other timing values, for calculation of appropriate memory access parameters.

Abstract: In a computer system having an audio circuit and networking circuit for data conferencing with an external network, a method of configuring the computer system for data conferencing includes the step of storing a plurality of data conferencing protocols. The method then determines which one of the plurality of data conferencing protocols is needed for the computer system for data conferencing. The computer system is then configured in accordance with a first protocol of the plurality of data conferencing protocols if the computer system is determined to require the first protocol for data conferencing. The method then selects an audio device driver and a networking device driver that correspond to the first protocol from a plurality of audio and networking device drivers for controlling operations of the audio and networking circuits.

Abstract: A method and apparatus for sharing a logic block between multiple peripheral/input/output I/O devices. A method and apparatus for generating a first interrupt in response to a request from one of the devices. A second interrupt is also generated. The second interrupt is recognized before the first interrupt, such that the second interrupt is handled first and causes the logic block to be configured for the requested device. Then the first interrupt is then handled in which the request to the desired device is serviced using the reconfigured hardware.

Abstract: A method and apparatus for performing fly-by transfer in a memory subsystem of a computer system. The present invention transfers data between a display memory and the system memory in the memory subsystem using common data and address buses. To complete a transfer between the two, the RAS is activated for both the display and system memory banks and then the CAS signal is cycled for both the display memory and the system memory, thereby causing a page mode transfer of the data between the two memories without having to use the system bus of the computer system.

Abstract: A power management mechanism for use in a computer system having a bus, a memory for storing data and instructions, and a central processing unit (CPU). The CPU runs an operating system having a power management virtual device driver (PMVxD) responsible for performing idle detection for devices. The PMVxD performs idle detection using event timers that provide an indicator as to the activity level. The PMVxD places idle local devices in a reduced power consumption state when no activity has occurred for a predetermined period of time.

Abstract: A method and apparatus for emulating circuitry in a computer system is described. The method and apparatus includes a method and apparatus for determining when the circuit is to be accessed. Furthermore, in the currently preferred embodiment, the present invention includes a method and apparatus for trapping the address and data of the access. The present invention also includes a method and apparatus for generating an interrupt transparently indicating to the computer system that the circuitry is being accessed. The present invention also includes a method and apparatus for handling the interrupt and emulating the function of the circuitry. In the currently preferred embodiment, the method and apparatus for emulating comprises a software routine.

Abstract: A symmetric multiprocessing system with a unified environment and distributed system functions provides unified address space for all functional units in the system while distributing the execution of various system functions over the functional units of the system whereby each functional unit assumes responsibility for its own aspects of these operations. In addition, the system provides improved system bus operation for transfer of data from memory.

Abstract: The present invention discloses a method and apparatus for minimizing the number of pins required in a memory system for support of partial word write operations to an ECC protected memory array. A memory system is provided having a memory controller which is coupled to a system bus via a first control bus and to an ECC protected memory array via a second control bus. The memory system also includes a data path buffer which is similarly connected to the system bus via a first data bus and to the memory array via a second data bus. Furthermore, a first control bus is coupled between the memory controller and the data path buffer. A byte enable bus is provided for transmitting eight byte enable signals therebetween. A multiplexor and a demultiplexor are arranged at the respective ends of the byte enable bus for multiplexing and demultiplexing the signals as they are transmitted.

Abstract: A method of handling invalid data being transmitted from a first agent to a second agent. If the first agent determines that the data it is to transmit is invalid data, then the first agent transmits an error signal to the second agent indicating invalid data. The first agent then attempts to correct the invalid data, and transmits the attempted corrected invalid data to the second agent after a predetermined period of time. Thereafter, the first agent transmits any remaining data not yet transmitted. If the second agent receives the error signal, then it suspends reading data for the predetermined period, and thereafter resumes reading data.

Abstract: A power management mechanism for use in a computer system having a bus, a memory for storing data and instructions, and a central processing unit (CPU). The CPU runs an operating system having a power management virtual device driver (PMV×D) responsible for performing idle detection for devices. The PMV×D performs idle detection using event timers that provide an indicator as to the activity level. The PMV×D places idle local devices in a reduced power consumption state when no activity has occurred for a predetermined period of time.

Abstract: A power management mechanism for use in a computer system having a bus, a memory for storing data and instructions, and a central processing unit (CPU). The CPU runs an operating system having a power management virtual device driver (PMV×D) responsible for performing idle detection for devices. The PMV×D performs idle detection using event timers that provide an indicator as to the activity level. The PMV×D places idle local devices in a reduced power consumption state when no activity has occurred for a predetermined period of time.