Abstract: Systems and methods are disclosed to automatically design a custom integrated circuit includes receiving a specification of the custom integrated circuit including computer readable code and one or more constraints on the custom integrated circuit; automatically devising a processor architecture and generating a processor chip specification uniquely customized to the computer readable code which satisfies the constraints; and synthesizing the chip specification into a layout of the custom integrated circuit.

Abstract: Systems and methods are disclosed to manage power in a custom integrated circuit (IC) design by receiving a specification of the custom integrated circuit including computer readable code and generating a profile of the computer readable code to determine instruction usage; automatically generating a processor architecture uniquely customized to the computer readable code, the processor architecture having one or more processing blocks and one or more power domains; determining when each processing block is needed based on the code profile and assigning each block to one of the power domains; and gating the power domains with power based on the code profile; and synthesizing the generated architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication.

Abstract: Systems and methods are disclosed to automatically generate a custom integrated circuit (IC) design by receiving a specification of the custom IC including computer readable code to be executed by the custom IC; generating an abstraction of the IC as a system, processor architecture and micro-architecture (SAMA) representation; providing the SAMA representation to a data model having at least an architecture optimization view, a physical design view, and a software tool view; optimizing the processor architecture by iteratively updating the SAMA representation and the data model to automatically generate a processor architecture uniquely customized to the computer readable code which satisfies one or more constraints; and synthesizing the generated architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication. The foregoing can be done with no or minimal human involvement.

Abstract: In some embodiments, the execution of load and store instructions for internal fields of data structures is accelerated by using on-chip template registers and appropriate machine code instructions. A load/store machine code instruction comprises an identifier of a memory address offset of an internal field word relative to a base address of the data structure, an identifier of an intra-word start bit of the internal field, and an identifier of an intra-word length of the internal field. The three identifiers may coincide, for example if the three identifiers are represented by an identity of a template register storing a template entry including the memory address offset, the start position, and the field length. The three identifiers may also be provided as part of a machine code instruction itself. Further provided are compilers, compiler methods, and hardware systems for implementing accelerated internal-field load and store operations.