Abstract: A processor coupled to an AIPR-enabled NAND memory device comprising an n by m array of dies having n channels, each die having first and second independently accessible planes, receives read commands including instructions to access data on planes of a die. The processor determines the destination die plane of the command and sends the command to a die plane queue based on the determined destination die plane. The processor fetches commands from a head of a first die plane queue for a first plane of the destination die and a head of a second die plane queue for the second plane of the destination die, and performs reads at both the first and second planes of the destination die in parallel based on the commands.