Abstract: A method for determining the setup and hold times of static flip-flops during the design and development of integrated circuits. The method utilizes simulations of an integrated circuit to determine a first amount of time required for a data signal to be transmitted from a first external node to a predetermined node in the register of a static flip-flop, and a second amount of time required for a clock signal to be transmitted from a second external node to the predetermined node. The setup time is determined by calculating a difference between the first amount of time from the second amount of time. Similarly, a hold time for the flip-flop is determined by calculating a difference between the amounts of time required for data and the clock signal to reach a second predetermined internal node of the flip-flop.

Abstract: Method and system for testing building blocks or cells stored in cell libraries used in digital design including generating a test design configuration of rows and columns of cells of the particular cell library and interconnecting each pin of each cell in the test design for isolating and correcting faulty cells in the cell library such that error check at the cell level and simultaneously checking errors in the cell library is provided.

Abstract: The disclosure teaches reducing capacitive interference (also referred to as the Miller effect) in an integrated circuit having at least two conductors. One repeater is located on a first conductor and two repeaters are located on a second conductor. The two repeaters on the second conductor are located to on each side of the repeater on the first conductor. Locating the two repeaters on the second conductor on each side of the repeater on the first conductor balances or offsets the capacitive effect. In an embodiment, two repeaters on the second conductor are spaced substantially equidistantly from one repeater on the first conductor.

Abstract: A method for determining the setup and hold times of static flip-flops during the design and development of integrated circuits. The method utilizes simulations of an integrated circuit to determine a first amount of time required for a data signal to be transmitted from a first external node to a predetermined node in the register of a static flip-flop, and a second amount of time required for a clock signal to be transmitted from a second external node to the predetermined node. The setup time is determined by calculating a difference between the first amount of time from the second amount of time. Similarly, a hold time for the flip-flop is determined by calculating a difference between the amounts of time required for data and the clock signal to reach a second predetermined internal node of the flip-flop.

Abstract: A method for determining the setup and hold times of static flip-flops during the design and development of integrated circuits. The method utilizes simulations of an integrated circuit to determine a first amount of time required for a data signal to be transmitted from a first external node to a predetermined node in the register of a static flip-flop, and a second amount of time required for a clock signal to be transmitted from a second external node to the predetermined node. The setup time is determined by calculating a difference between the first amount of time from the second amount of time. Similarly, a hold time for the flip-flop is determined by calculating a difference between the amounts of time required for data and the clock signal to reach a second predetermined internal node of the flip-flop.

Abstract: A method for testing sequential circuit designs in which an exhaustive sequence of test vectors is applied to the input nodes of edge-sensitive components of a simulated sequential circuit. The test vector values are selected from a group including a logic “1” (high), a logic “0” (low), a “floating” value (i.e., between logic “1” and logic “0”) and a randomly generated (“don't care”) value. While a predetermined combination of values is applied to all other input nodes of the simulated circuit, the sequence of test vector values is applied to a selected input node that produces all possible transitions between the test vector values. The predetermined combination of values applied to all other input nodes is then incrementally changed, and the test vector value sequence is repeated.

Abstract: A testing method in which the stages in a multi-stage counter chain are tested sequentially. A counter chain is composed of two or more stages with the carry-out signal from each stage being coupled to the carry-in signal of a subsequent stage. Various circuit modules may be clocked from intermediate stages in the counter chain. In the test mode, the carry-out signal from a given stage is latched once it is asserted. Thereafter, the subsequent stage counts at a higher rate. In this manner, each stage of the chain is run through a complete count, thus verifying the functionality of each stage. Further, the first stage finishes a complete count cycle before the second stage begins counting at a higher rate. A circuit module which is clocked by the output of the first stage is therefore able to complete an operation before any circuit modules clocked by subsequent stages are triggered.