Abstract: Systems and methods for emulate or prototyping of hardware, such as memory, are disclosed. A memory compiler may receive information, such as system calls, indicative of one or more aspects of latency. Responsive to the information, the memory compiler may create infrastructure, such as pipelines and FIFOs, based on the aspects of latency, for emulation or prototyping of the hardware. Using the created infrastructure may improve emulation compile speed, such as by creating a pipeline-based cache structure, and may improve emulation runtime speed, such as by utilizing earlier unused model clocks to fetch data from host sooner.

Abstract: In one example in accordance with the present disclosure an apparatus for attaching to a shaft using a wedge is described. The apparatus includes a disc having a longitudinal axis. At least a portion of the disc is insertable into a shaft and is expandable against an inside diameter of the shaft. The disc has a recess at the longitudinal axis. A wedge to be inserted into the recess pushes the portion of the disc that is insertable into the shaft against an inside diameter of the shaft.

Abstract: Messages transmitted from an emulator to a testbench of a part of the testbench are recorded from a starting point of an emulation operation to a checkpoint of the emulation operation. State information of the emulator at the checkpoint is captured and stored. The emulator is then configured to a state corresponding to the checkpoint based on the stored state information, and the testbench or the part of the testbench is restored to the checkpoint by running the testbench or the part of the testbench based on the recorded messages.

Abstract: Aspects of the disclosed technology relate to techniques of bandwidth test in networking system-on-chip design verification. A hardware model of interface circuitry implemented in a reconfigurable hardware modeling device associates dispatch time information with messages when the messages are dispatched by a hardware model of a circuit design implemented in the reconfigurable hardware modeling device. The dispatch time information of a particular message includes information about when, based on a model time reference provided in the reconfigurable hardware modeling device, the particular message is dispatched by the hardware model of the circuit design. The messages and the dispatch time information are sent to a traffic analysis device, which determines bandwidth information of ports of the circuit design based on the dispatch time information.

Abstract: Aspects of the disclosed technology relate to techniques of latency test in networking system-on-chip design verification. A hardware model of interface circuitry implemented in a reconfigurable hardware modeling device associates arrival time information with messages when the messages are delivered to a hardware model of a circuit design implemented in the reconfigurable hardware modeling device, and associates latency information with the messages when the messages are dispatched by the hardware model of the circuit design. The arrival time information of a particular message and the latency information are determined with respect to a model time reference provided in the reconfigurable hardware modeling device.

Abstract: A system for verifying networking system-on-chip designs comprises a reconfigurable hardware modeling device programmed to implement circuitry hardware models and a traffic generation device communicating with the reconfigurable hardware modeling device. The circuitry hardware models comprise a hardware model of a circuit design and a hardware model of interface circuitry. The system employs a backpressure flow control independent of the communication protocol, which can cause the traffic generation device to suspend sending messages when one or more message buffers in the traffic generation device, the reconfigurable hardware modeling device, or both cannot accept more messages based on predetermined conditions.

Abstract: In one example in accordance with the present disclosure an apparatus for attaching to a shaft using a wedge is described. The apparatus includes a disc having a longitudinal axis. At least a portion of the disc is insertable into a shaft and is expandable against an inside diameter of the shaft. The disc has a recess at the longitudinal axis. A wedge to be inserted into the recess pushes the portion of the disc that is insertable into the shaft against an inside diameter of the shaft.

Abstract: A system is described for managing interaction between an untimed HAL portion and a timed HDL portion of the testbench, wherein the timed portion is embodied on an emulator and the un-timed portion executes on a workstation. Repeatability of verification results may be achieved even though the HAL portion and the HDL portion run in parallel with each other. A communication interface is also described for synchronizing and passing data between multiple HDL threads on the emulator domain and simultaneously-running multiple HAL threads on the workstation domain. In addition, a remote procedural-call-based communication link, transparent to the user, is generated between the workstation and the emulator. A technique provides for repeatability for blocking and non-blocking procedure calls. FSMs and synchronization logic are automatically inferred to implement remote procedural calls. A subset of behavioral language is identified that combines the power of conventional modeling paradigms with RTL performance.

Abstract: A system and method is presented for synthesizing both a design under test (DUT) and its test environment (i.e., the testbench for the DUT), into an equivalent structural model suitable for execution on a reconfigurable hardware platform. This may be achieved without any change in the existing verification methodology. Behavioral HDL may be translated into a form that can be executed on a reconfigurable hardware platform. A set of compilation transforms are provided that convert behavioral constructs into RTL constructs that can be directly mapped onto an emulator. Such transforms are provided by introducing the concepts of a behavioral clock and a time advance finite state machine (FSM) that determines simulation time and sequences concurrent computing blocks in the DUT and the testbench.

Abstract: An application interface provides an environment in which applications may discover and attach to data streams. The interface facilitates efficient sharing and management of acquired data through arbitration and parallel processing: allowing multiple applications to work in parallel on the same or different data streams to implement independent or co-dependent functionality. Further, the interface acts as a bridge between system address spaces allowing applications to execute in their own address space separate from the resource intensive acquisition processes. The interface also provides an environment for prototyping applications where a user may allocate data streams to an application and debug the application's execution. Because the interface provides a standardized/normalized interface to the acquired image data, applications may be developed independent of the imaging system's implementation details, data formats and protocols.

Abstract: A system is described for managing interaction between an untimed HAL portion and a timed HDL portion of the testbench, wherein the timed portion is embodied on an emulator and the un-timed portion executes on a workstation. Repeatability of verification results may be achieved even though the HAL portion and the HDL portion run in parallel with each other. A communication interface is also described for synchronizing and passing data between multiple HDL threads on the emulator domain and simultaneously-running multiple HAL threads on the workstation domain. In addition, a remote procedural-call-based communication link, transparent to the user, is generated between the workstation and the emulator. A technique provides for repeatability for blocking and non-blocking procedure calls. FSMs and synchronization logic are automatically inferred to implement remote procedural calls. A subset of behavioral language is identified that combines the power of conventional modeling paradigms with RTL performance.

Abstract: A system and method is presented for synthesizing both a design under test (DUT) and its test environment (i.e., the testbench for the DUT), into an equivalent structural model suitable for execution on a reconfigurable hardware platform. This may be achieved without any change in the existing verification methodology. Behavioral HDL may be translated into a form that can be executed on a reconfigurable hardware platform. A set of compilation transforms are provided that convert behavioral constructs into RTL constructs that can be directly mapped onto an emulator. Such transforms are provided by introducing the concepts of a behavioral clock and a time advance finite state machine (FSM) that determines simulation time and sequences concurrent computing blocks in the DUT and the testbench.

Abstract: A method of pre-analyzing video signals obtained from a digital image stores the digital image in a frame buffer store in a specified video digital format. The amplitude, saturation and frequency of the stored digital image when converted into another video format, such as RGB or composite broadcast video, are each analyzed independently to identify areas of the stored digital image that might produce distortions in the final video format when displayed. Amplitude analysis is accomplished by converting the stored digital image into an RGB image, and each component is compared with predetermined limits to detect amplitude errors. Saturation analysis is accomplished by generating a saturation signal from the chrominance components of the stored digital image, and then comparing a function of the saturation signal with predetermined limits to detect oversaturation errors.