Patents by Inventor Suresh Kumar Venkumahanti
Suresh Kumar Venkumahanti has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11663011Abstract: Very long instruction word (VLIW) instruction processing using a reduced-width processor is disclosed. In a particular embodiment, a VLIW processor includes a control circuit configured to receive a VLIW packet that includes a first number of instructions and to distribute the instructions to a second number of instruction execution paths. The first number is greater than the second number. The VLIW processor also includes physical registers configured to store results of executing the instructions and a register renaming circuit that is coupled to the control circuit.Type: GrantFiled: July 7, 2020Date of Patent: May 30, 2023Assignee: Qualcomm IncorporatedInventors: Peter Sassone, Christopher Koob, Suresh Kumar Venkumahanti
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Patent number: 11599625Abstract: Methods, systems, and devices for techniques for instruction perturbation for improved device security are described. A device may assign a set of executable instructions to an instruction packet based on a parameter associated with the instruction packet, and each executable instruction of the set of executable instructions may be independent from other executable instructions of the set of executable instructions. The device may select an order of the set of executable instructions based on a slot instruction rule associated with the device, and each executable instruction of the set of executable instructions may correspond to a respective slot associated with memory of the device. The device may modify the order of the set of executable instructions in a memory hierarchy post pre-decode based on the slot instruction rule and process the set of executable instructions of the instruction packet based on the modified order.Type: GrantFiled: January 28, 2021Date of Patent: March 7, 2023Assignee: QUALCOMM IncorporatedInventors: Arvind Krishnaswamy, Suresh Kumar Venkumahanti, Charles Tabony
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Publication number: 20220237283Abstract: Methods, systems, and devices for techniques for instruction perturbation for improved device security are described. A device may assign a set of executable instructions to an instruction packet based on a parameter associated with the instruction packet, and each executable instruction of the set of executable instructions may be independent from other executable instructions of the set of executable instructions. The device may select an order of the set of executable instructions based on a slot instruction rule associated with the device, and each executable instruction of the set of executable instructions may correspond to a respective slot associated with memory of the device. The device may modify the order of the set of executable instructions in a memory hierarchy post pre-decode based on the slot instruction rule and process the set of executable instructions of the instruction packet based on the modified order.Type: ApplicationFiled: January 28, 2021Publication date: July 28, 2022Inventors: Arvind KRISHNASWAMY, Suresh Kumar VENKUMAHANTI, Charles TABONY
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Patent number: 11200058Abstract: Dynamic load balancing of hardware threads in clustered processor cores using shared hardware resources, and related circuits, methods, and computer readable media are disclosed. In one aspect, a dynamic load balancing circuit comprising a control unit is provided. The control unit is configured to determine whether a suboptimal load condition exists between a first cluster and a second cluster of a clustered processor core. If a suboptimal load condition exists, the control unit is further configured to transfer a content of private register(s) of a first hardware thread of the first cluster to private register(s) of a second hardware thread of the second cluster via shared hardware resources of the first hardware thread and the second hardware thread. The control unit is also configured to exchange a first identifier associated with the first hardware thread with a second identifier associated with the second hardware thread via the shared hardware resources.Type: GrantFiled: May 7, 2014Date of Patent: December 14, 2021Inventors: Suresh Kumar Venkumahanti, Stephen Robert Shannon, Lin Wang
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Patent number: 11074076Abstract: Dynamic load balancing of hardware threads in clustered processor cores using shared hardware resources, and related circuits, methods, and computer readable media are disclosed. In one aspect, a dynamic load balancing circuit comprising a control unit is provided. The control unit is configured to determine whether a suboptimal load condition exists between a first cluster and a second cluster of a clustered processor core. If a suboptimal load condition exists, the control unit is further configured to transfer a content of private register(s) of a first hardware thread of the first cluster to private register(s) of a second hardware thread of the second cluster via shared hardware resources of the first hardware thread and the second hardware thread. The control unit is also configured to exchange a first identifier associated with the first hardware thread with a second identifier associated with the second hardware thread via the shared hardware resources.Type: GrantFiled: May 7, 2014Date of Patent: July 27, 2021Assignee: QUALCOMM IncorporatedInventors: Suresh Kumar Venkumahanti, Stephen Robert Shannon, Lin Wang
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Publication number: 20200364051Abstract: Very long instruction word (VLIW) instruction processing using a reduced-width processor is disclosed. In a particular embodiment, a VLIW processor includes a control circuit configured to receive a VLIW packet that includes a first number of instructions and to distribute the instructions to a second number of instruction execution paths. The first number is greater than the second number. The VLIW processor also includes physical registers configured to store results of executing the instructions and a register renaming circuit that is coupled to the control circuit.Type: ApplicationFiled: July 7, 2020Publication date: November 19, 2020Inventors: Peter SASSONE, Christopher KOOB, Suresh Kumar VENKUMAHANTI
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Patent number: 10719325Abstract: Very long instruction word (VLIW) instruction processing using a reduced-width processor is disclosed. In a particular embodiment, a VLIW processor includes a control circuit configured to receive a VLIW packet that includes a first number of instructions and to distribute the instructions to a second number of instruction execution paths. The first number is greater than the second number. The VLIW processor also includes physical registers configured to store results of executing the instructions and a register renaming circuit that is coupled to the control circuit.Type: GrantFiled: November 7, 2017Date of Patent: July 21, 2020Assignee: Qualcomm IncorporatedInventors: Peter Sassone, Christopher Koob, Suresh Kumar Venkumahanti
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Patent number: 10625752Abstract: A system and a method for error-correction code (“ECC”) error handling is described herein. In one aspect, the system and method may operate an ECC function on raw data. The ECC function may include generating ECC syndrome data by an ECC syndrome data generating module. The ECC syndrome data may be derived from the raw data. The system and a method may further inject a fault based on the ECC syndrome data or the raw data. The system and a method may further determine whether the ECC error detected by the ECC checker corresponds to a malfunction of the ECC function or the fault injected based on the ECC syndrome data or the raw data.Type: GrantFiled: December 12, 2017Date of Patent: April 21, 2020Assignee: Qualcomm IncorporatedInventors: Mohammad Reza Kakoee, Rahul Gulati, Eric Mahurin, Suresh Kumar Venkumahanti, Dexter Chun
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Patent number: 10353447Abstract: A programmable logic circuit such as a finite state machine is provided that is configured to determine a memory array power-up sequence from a configuration signal to successively enable each memory array. A delay circuit triggers an initial memory bank in each enabled memory array to power-up without a delay. The delay circuit then counts responsive to a clock to determine a delay between a successive triggering of remaining memory banks in each enabled memory array to power-up.Type: GrantFiled: March 3, 2017Date of Patent: July 16, 2019Assignee: QUALCOMM IncorporatedInventors: Harmander Singh, Sebastien Weyland, Suresh Kumar Venkumahanti
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Publication number: 20190196867Abstract: A processor includes priority adjustment circuitry configured to adjust a priority of a thread of multiple threads configured to execute tasks to have a software-defined priority value or a designated high priority value. The processor also includes circuitry configured to identify a lowest priority thread of the multiple threads and a control unit configured to cause the lowest priority thread to take a pending interrupt.Type: ApplicationFiled: May 18, 2018Publication date: June 27, 2019Inventors: Erich Plondke, Suresh Kumar Venkumahanti, Lin Wang, Lucian Codrescu
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Publication number: 20190176838Abstract: A system and a method for error-correction code (“ECC”) error handling is described herein. In one aspect, the system and method may operate an ECC function on raw data. The ECC function may include generating ECC syndrome data by an ECC syndrome data generating module. The ECC syndrome data may be derived from the raw data. The system and a method may further inject a fault based on the ECC syndrome data or the raw data. The system and a method may further determine whether the ECC error detected by the ECC checker corresponds to a malfunction of the ECC function or the fault injected based on the ECC syndrome data or the raw data.Type: ApplicationFiled: December 12, 2017Publication date: June 13, 2019Inventors: Mohammad Reza KAKOEE, Rahul Gulati, Eric Mahurin, Suresh Kumar Venkumahanti, Dexter Chun
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Publication number: 20190138311Abstract: Very long instruction word (VLIW) instruction processing using a reduced-width processor is disclosed. In a particular embodiment, a VLIW processor includes a control circuit configured to receive a VLIW packet that includes a first number of instructions and to distribute the instructions to a second number of instruction execution paths. The first number is greater than the second number. The VLIW processor also includes physical registers configured to store results of executing the instructions and a register renaming circuit that is coupled to the control circuit.Type: ApplicationFiled: November 7, 2017Publication date: May 9, 2019Inventors: Peter SASSONE, Christopher KOOB, Suresh Kumar VENKUMAHANTI
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Publication number: 20180253129Abstract: A programmable logic circuit such as a finite state machine is provided that is configured to determine a memory array power-up sequence from a configuration signal to successively enable each memory array. A delay circuit triggers an initial memory bank in each enabled memory array to power-up without a delay. The delay circuit then counts responsive to a clock to determine a delay between a successive triggering of remaining memory banks in each enabled memory array to power-up.Type: ApplicationFiled: March 3, 2017Publication date: September 6, 2018Inventors: Harmander Singh, Sebastien Weyland, Suresh Kumar Venkumahanti
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Patent number: 10068645Abstract: In an aspect of the disclosure, a method and an apparatus are provided. The apparatus may be a content addressable memory. The content addressable memory includes a plurality of memory sections each configured to store data. Additionally, the content addressable memory includes a comparator configured to compare the stored data in each of the plurality of memory sections with search input data. The comparison may be in a time division multiplexed fashion. The comparator may be configured to compare the stored data in each of the plurality of memory sections with search input data in a corresponding one of a plurality of memory access cycles. The content addressable memory may include a state machine configured to control when the comparator compares the stored data in each of the plurality of memory sections with search input data based on a state of the state machine.Type: GrantFiled: December 5, 2016Date of Patent: September 4, 2018Assignee: QUALCOMM IncorporatedInventors: Kim Yaw Tong, Suresh Kumar Venkumahanti, Fadi Hamdan, Kun Ma
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Patent number: 10007613Abstract: An apparatus includes an access mode selection circuit configured to select a cache access mode based on a number of instructions stored at an issue queue, a number of active threads of an execution unit coupled to a cache, or both. The access mode selection circuit is further configured to generate an access mode signal based on the selected cache access mode. The apparatus further includes an address generation circuit configured to perform a cache access based on the access mode signal.Type: GrantFiled: July 15, 2016Date of Patent: June 26, 2018Assignee: QUALCOMM IncorporatedInventors: Suresh Kumar Venkumahanti, Stephen Robert Shannon
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Publication number: 20180081815Abstract: Systems and methods for accessing a cache include determining if a current access of the cache will satisfy an expected relationship with a next access of the cache, wherein the cache is a set-associative cache comprising multiple ways. The next way for the next access is stored in a next way field associated with the current access. If the expected relationship will be satisfied, such as a sequential relationship which will be satisfied in the case of an instruction cache when the current access does not cause a change in control flow, the next way for the next access is retrieved from the next way field associated with the current access. The next way of the cache is then directly accessed using the retrieved next way.Type: ApplicationFiled: September 22, 2016Publication date: March 22, 2018Inventors: Suresh Kumar VENKUMAHANTI, Aditi GORE, Stephen SHANNON, Matthew CUMMINGS
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Publication number: 20170345500Abstract: In an aspect of the disclosure, a method and an apparatus are provided. The apparatus may be a content addressable memory. The content addressable memory includes a plurality of memory sections each configured to store data. Additionally, the content addressable memory includes a comparator configured to compare the stored data in each of the plurality of memory sections with search input data. The comparison may be in a time division multiplexed fashion. The comparator may be configured to compare the stored data in each of the plurality of memory sections with search input data in a corresponding one of a plurality of memory access cycles. The content addressable memory may include a state machine configured to control when the comparator compares the stored data in each of the plurality of memory sections with search input data based on a state of the state machine.Type: ApplicationFiled: December 5, 2016Publication date: November 30, 2017Inventors: Kim Yaw TONG, Suresh Kumar VENKUMAHANTI, Fadi HAMDAN, Kun MA
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Publication number: 20170249146Abstract: Systems and methods pertain to reducing bandwidth of instruction tracing for a processor, using an Embedded Trace Macrocell (ETM). Packets, which include trace information for load/store instructions executed in the processor, are generated. A P-Header comprising commit information for load/store instructions of up to a maximum number of two or more packets is generated. The P-Header is generated for the maximum number of two or more packets if none of the load/store instructions in the maximum number of two or more packets were killed. If a load/store instruction in a packet was killed, a P-Header comprising commit information for the packet comprising the load/store instruction which was killed is generated and placed in an instruction trace immediately after that packet, even if the maximum number is not reached.Type: ApplicationFiled: February 29, 2016Publication date: August 31, 2017Inventors: Suresh Kumar VENKUMAHANTI, Venkatarami MORA
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Patent number: 9715392Abstract: A method includes identifying, at a scheduling unit, a resource conflict at a shared processing resource that is accessible by a first processing cluster and by a second processing cluster, where the first processing cluster, the second processing cluster, and the shared processing resource are included in a very long instruction word (VLIW) processing unit. The method also includes resolving the resource conflict.Type: GrantFiled: August 29, 2014Date of Patent: July 25, 2017Assignee: QUALCOMM IncorporatedInventors: Suresh Kumar Venkumahanti, Ankit Ghiya, Peter Gene Sassone, Lucian Codrescu, Suman Mamidi
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Patent number: 9678758Abstract: Systems and methods for implementing certain load instructions, such as vector load instructions by cooperation of a main processor and a coprocessor. The load instructions which are identified by the main processor for offloading to the coprocessor are committed in the main processor without receiving corresponding load data. Post-commit, the load instructions are processed in the coprocessor, such that latencies incurred in fetching the load data are hidden from the main processor. By implementing an out-of-order load data buffer associated with an in-order instruction buffer, the coprocessor is also configured to avoid stalls due to long latencies which may be involved in fetching the load data from levels of memory hierarchy, such as L2, L3, L4 caches, main memory, etc.Type: GrantFiled: September 26, 2014Date of Patent: June 13, 2017Assignee: QUALCOMM IncorporatedInventors: Lucian Codrescu, Christopher Edward Koob, Eric Wayne Mahurin, Suresh Kumar Venkumahanti