Patents by Inventor Suresh N. Rajan
Suresh N. Rajan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9575835Abstract: A dynamic random access memory (DRAM) array is configured for selective repair and error correction of a subset of the array. Error-correcting code (ECC) is provided to a selected subset of the array to protect a row or partial row of memory cells where one or more weak memory cells are detected. By adding a sense amplifier stripe to the edge of the memory array, the adjacent edge segment of the array is employed to store ECC information associated with the protected subsets of the array. Bit replacement is also applied to defective memory cells. By implementing ECC selectively rather than to the entire array, integrity of the memory array is maintained at minimal cost to the array in terms of area and energy consumption.Type: GrantFiled: April 21, 2015Date of Patent: February 21, 2017Assignee: Rambus Inc.Inventors: Thomas Vogelsang, Suresh N. Rajan, Ian P. Shaeffer, Frederick A. Ware, Wayne F. Ellis
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Publication number: 20150234707Abstract: A dynamic random access memory (DRAM) array is configured for selective repair and error correction of a subset of the array. Error-correcting code (ECC) is provided to a selected subset of the array to protect a row or partial row of memory cells where one or more weak memory cells are detected. By adding a sense amplifier stripe to the edge of the memory array, the adjacent edge segment of the array is employed to store ECC information associated with the protected subsets of the array. Bit replacement is also applied to defective memory cells. By implementing ECC selectively rather than to the entire array, integrity of the memory array is maintained at minimal cost to the array in terms of area and energy consumption.Type: ApplicationFiled: April 21, 2015Publication date: August 20, 2015Inventors: Thomas Vogelsang, Suresh N. Rajan, Ian P. Shaeffer, Frederick A. Ware, Wayne F. Ellis
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Patent number: 9037949Abstract: A dynamic random access memory (DRAM) array is configured for selective repair and error correction of a subset of the array. Error-correcting code (ECC) is provided to a selected subset of the array to protect a row or partial row of memory cells where one or more weak memory cells are detected. By adding a sense amplifier stripe to the edge of the memory array, the adjacent edge segment of the array is employed to store ECC information associated with the protected subsets of the array. Bit replacement is also applied to defective memory cells. By implementing ECC selectively rather than to the entire array, integrity of the memory array is maintained at minimal cost to the array in terms of area and energy consumption.Type: GrantFiled: March 18, 2013Date of Patent: May 19, 2015Assignee: Rambus Inc.Inventors: Thomas Vogelsang, Suresh N. Rajan, Ian P. Shaeffer, Frederick A. Ware, Wayne F. Ellis
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Patent number: 8619452Abstract: Large capacity memory systems are constructed using stacked memory integrated circuits or chips. The stacked memory chips are constructed in such a way that eliminates problems such as signal integrity while still meeting current and future memory standards.Type: GrantFiled: September 1, 2006Date of Patent: December 31, 2013Assignee: Google Inc.Inventors: Suresh N. Rajan, Michael J. S. Smith, David T Wang
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Publication number: 20130103896Abstract: A memory module, which includes at least one memory stack, comprises a plurality of DRAM integrated circuits and an interface circuit. The interface circuit interfaces the memory stack to a host system so as to operate the memory stack as a single DRAM integrated circuit. In other embodiments, a memory module includes at least one memory stack and a buffer integrated circuit. The buffer integrated circuit, coupled to a host system, interfaces the memory stack to the host system so to operate the memory stack as at least two DRAM integrated circuits. In yet other embodiments, the buffer circuit interfaces the memory stack to the host system for transforming one or more physical parameters between the DRAM integrated circuits and the host system.Type: ApplicationFiled: September 14, 2012Publication date: April 25, 2013Applicant: GOOGLE INC.Inventors: Suresh N. Rajan, Keith R. Schakel, Michael J.S. Smith, David T. Wang, Frederick Daniel Weber
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Publication number: 20130100746Abstract: Large capacity memory systems are constructed using stacked memory integrated circuits or chips. The stacked memory chips are constructed in such a way that eliminates problems such as signal integrity while still meeting current and future memory standards.Type: ApplicationFiled: September 14, 2012Publication date: April 25, 2013Applicant: GOOGLE INC.Inventors: Suresh N. Rajan, Michael J. S. Smith, David T. Wang
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Publication number: 20120268982Abstract: Large capacity memory systems are constructed using stacked memory integrated circuits or chips. The stacked memory chips are constructed in such a way that eliminates problems such as signal integrity while still meeting current and future memory standards.Type: ApplicationFiled: June 28, 2012Publication date: October 25, 2012Applicant: GOOGLE INC.Inventor: Suresh N. Rajan
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Publication number: 20120102292Abstract: A memory module, which includes at least one memory stack, comprises a plurality of DRAM integrated circuits and an interface circuit. The interface circuit interfaces the memory stack to a host system so as to operate the memory stack as a single DRAM integrated circuit. In other embodiments, a memory module includes at least one memory stack and a buffer integrated circuit. The buffer integrated circuit, coupled to a host system, interfaces the memory stack to the host system so to operate the memory stack as at least two DRAM integrated circuits. In yet other embodiments, the buffer circuit interfaces the memory stack to the host system for transforming one or more physical parameters between the DRAM integrated circuits and the host system.Type: ApplicationFiled: December 30, 2011Publication date: April 26, 2012Applicant: GOOGLE INC.Inventors: Suresh N. Rajan, Keith R. Schakel, Michael J.S. Smith, David T. Wang, Frederick Daniel Weber
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Patent number: 8089795Abstract: A memory module, which includes at least one memory stack, comprises a plurality of DRAM integrated circuits and an interface circuit. The interface circuit interfaces the memory stack to a host system so as to operate the memory stack as a single DRAM integrated circuit. In other embodiments, a memory module includes at least one memory stack and a buffer integrated circuit. The buffer integrated circuit, coupled to a host system, interfaces the memory stack to the host system so to operate the memory stack as at least two DRAM integrated circuits. In yet other embodiments, an interface circuit maps virtual addresses from the host system to physical addresses of the DRAM integrated circuits in a linear manner. In a further embodiment, the interface circuit maps one or more banks of virtual addresses from the host system to a single one of the DRAM integrated circuits.Type: GrantFiled: February 5, 2007Date of Patent: January 3, 2012Assignee: Google Inc.Inventors: Suresh N. Rajan, Keith R Schakel, Michael J. S. Smith, David T Wang, Frederick Daniel Weber
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Publication number: 20110310686Abstract: A memory device comprises a first and second integrated circuit dies. The first integrated circuit die comprises a memory core as well as a first interface circuit. The first interface circuit permits full access to the memory cells (e.g., reading, writing, activating, pre-charging and refreshing operations to the memory cells). The second integrated circuit die comprises a second interface that interfaces the memory core, via the first interface circuit, an external bus, such as a synchronous interface to an external bus. A technique combines memory core integrated circuit dies with interface integrated circuit dies to configure a memory device. A speed test on the memory core integrated circuit dies is conducted, and the interface integrated circuit die is electrically coupled to the memory core integrated circuit die based on the speed of the memory core integrated circuit die.Type: ApplicationFiled: June 21, 2011Publication date: December 22, 2011Applicant: GOOGLE INC.Inventor: Suresh N. Rajan
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Patent number: 7990746Abstract: A memory device comprises a first and second integrated circuit dies. The first integrated circuit die comprises a memory core as well as a first interface circuit. The first interface circuit permits full access to the memory cells (e.g., reading, writing, activating, pre-charging and refreshing operations to the memory cells). The second integrated circuit die comprises a second interface that interfaces the memory core, via the first interface circuit, an external bus, such as a synchronous interface to an external bus. A technique combines memory core integrated circuit dies with interface integrated circuit dies to configure a memory device. A speed test on the memory core integrated circuit dies is conducted, and the interface integrated circuit die is electrically coupled to the memory core integrated circuit die based on the speed of the memory core integrated circuit die.Type: GrantFiled: July 27, 2009Date of Patent: August 2, 2011Assignee: Google Inc.Inventor: Suresh N. Rajan
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Publication number: 20100020585Abstract: Large capacity memory systems are constructed using stacked memory integrated circuits or chips. The stacked memory chips are constructed in such a way that eliminates problems such as signal integrity while still meeting current and future memory standards.Type: ApplicationFiled: October 6, 2009Publication date: January 28, 2010Inventor: Suresh N. Rajan
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Publication number: 20090290442Abstract: A memory device comprises a first and second integrated circuit dies. The first integrated circuit die comprises a memory core as well as a first interface circuit. The first interface circuit permits full access to the memory cells (e.g., reading, writing, activating, pre-charging and refreshing operations to the memory cells). The second integrated circuit die comprises a second interface that interfaces the memory core, via the first interface circuit, an external bus, such as a synchronous interface to an external bus. A technique combines memory core integrated circuit dies with interface integrated circuit dies to configure a memory device. A speed test on the memory core integrated circuit dies is conducted, and the interface integrated circuit die is electrically coupled to the memory core integrated circuit die based on the speed of the memory core integrated circuit die.Type: ApplicationFiled: July 27, 2009Publication date: November 26, 2009Inventor: Suresh N. Rajan
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Patent number: 7599205Abstract: Large capacity memory systems are constructed using stacked memory integrated circuits or chips. The stacked memory chips are constructed in such a way that eliminates problems such as signal integrity while still meeting current and future memory standards.Type: GrantFiled: March 25, 2008Date of Patent: October 6, 2009Assignee: MetaRAM, Inc.Inventor: Suresh N. Rajan
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Patent number: 7515453Abstract: A memory device comprises a first and second integrated circuit dies. The first integrated circuit die comprises a memory core as well as a first interface circuit. The first interface circuit permits full access to the memory cells (e.g., reading, writing, activating, pre-charging and refreshing operations to the memory cells). The second integrated circuit die comprises a second interface that interfaces the memory core, via the first interface circuit, an external bus, such as a synchronous interface to an external bus. A technique combines memory core integrated circuit dies with interface integrated circuit dies to configure a memory device. A speed test on the memory core integrated circuit dies is conducted, and the interface integrated circuit die is electrically coupled to the memory core integrated circuit die based on the speed of the memory core integrated circuit die.Type: GrantFiled: June 23, 2006Date of Patent: April 7, 2009Assignee: MetaRAM, Inc.Inventor: Suresh N. Rajan
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Publication number: 20080170425Abstract: Large capacity memory systems are constructed using stacked memory integrated circuits or chips. The stacked memory chips are constructed in such a way that eliminates problems such as signal integrity while still meeting current and future memory standards.Type: ApplicationFiled: March 25, 2008Publication date: July 17, 2008Inventor: Suresh N. Rajan
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Publication number: 20080126690Abstract: A memory module, which includes at least one memory stack, comprises a plurality of DRAM integrated circuits and an interface circuit. The interface circuit interfaces the memory stack to a host system so as to operate the memory stack as a single DRAM integrated circuit. In other embodiments, a memory module includes at least one memory stack and a buffer integrated circuit. The buffer integrated circuit, coupled to a host system, interfaces the memory stack to the host system so to operate the memory stack as at least two DRAM integrated circuits. In yet other embodiments, an interface circuit maps virtual addresses from the host system to physical addresses of the DRAM integrated circuits in a linear manner. In a further embodiment, the interface circuit maps one or more banks of virtual addresses from the host system to a single one of the DRAM integrated circuits.Type: ApplicationFiled: February 5, 2007Publication date: May 29, 2008Inventors: Suresh N. Rajan, Frederick Daniel Weber
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Patent number: 7379316Abstract: Large capacity memory systems are constructed using stacked memory integrated circuits or chips. The stacked memory chips are constructed in such a way that eliminates problems such as signal integrity while still meeting current and future memory standards.Type: GrantFiled: September 1, 2006Date of Patent: May 27, 2008Assignee: MetaRAM, Inc.Inventor: Suresh N. Rajan
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Publication number: 20070195613Abstract: A memory module, which includes at least one memory stack, comprises a plurality of DRAM integrated circuits and an interface circuit. The interface circuit interfaces the memory stack to a host system so as to operate the memory stack as a single DRAM integrated circuit. In other embodiments, a memory module includes at least one memory stack and a buffer integrated circuit. The buffer integrated circuit, coupled to a host system, interfaces the memory stack to the host system so to operate the memory stack as at least two DRAM integrated circuits. In yet other embodiments, an interface circuit maps virtual addresses from the host system to physical addresses of the DRAM integrated circuits in a linear manner. In a further embodiment, the interface circuit maps one or more banks of virtual addresses from the host system to a single one of the DRAM integrated circuits.Type: ApplicationFiled: February 5, 2007Publication date: August 23, 2007Inventors: Suresh N. Rajan, Keith R. Schakel, Michael J.S. Smith, David T. Wang, Frederick Daniel Weber
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Patent number: 5905577Abstract: A probe beam is used to sample the waveform on an IC device under test (DUT) during each cycle of a test pattern applied to the DUT. A reference laser beam is also used to sample the DUT. For each cycle of the test pattern, the reference and probe beams sample the DUT at the same physical location, but at displaced times with respect to each other. Each reference measurement is made at a fixed time relative to the test pattern while the probe measurements are scanned through the test-pattern time portion of interest, in the manner normal to equivalent time sampling, to reconstruct the waveform. For each test cycle, the ratio of these two measurements is taken. The fluctuations of these ratios due to noise is greatly reduced as compared to fluctuations of the probe measurements taken alone. Thus, a smaller number of averages is required to reconstruct the waveform.Type: GrantFiled: March 15, 1997Date of Patent: May 18, 1999Assignee: Schlumberger Technologies, Inc.Inventors: Kenneth R. Wilsher, Suresh N. Rajan, William K. Lo