Patents by Inventor Suresh Pothukuchi

Suresh Pothukuchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • FPGA BASED PLATFORM FOR POST-SILICON VALIDATION OF CHIPLETS
    Publication number: 20230401130
    Abstract: One embodiment provides an apparatus comprising a circuit board; an active interposer coupled with the circuit board via a debug package, and a graphics processor die coupled with the active interposer via the debug package. The graphics processor die includes graphics processor resources configured to execute instructions for a multi-die system on chip (SoC) device and excludes functionality that is implemented in a separate due of the multi-die SoC. The apparatus includes a field-programmable gate array (FPGA) including hardware logic that is configurable to emulate functionality provided by the separate die of the multi-die SoC device, which enables silicon validation of the graphics processor die separately from other dies of the multi-die SoC.
    Type: Application
    Filed: June 14, 2022
    Publication date: December 14, 2023
    Applicant: Intel Corporation
    Inventors: Rakesh Mehta, Hanmanthrao Patli, Ivan Herrera Mejia, Raj Chandar Rasappan, Hagay Spector, Renu Patle, Fylur Rahman Sathakathulla, Ruchira Liyanage, Raju Kasturi, Fred Steinberg, Ananth Gopalakrishnan, Satish Venkatesan, Pradyumna Reddy Patnam, Suresh Pothukuchi, Tapan Ganpule, Atthar H. Mohammed, Altug Koker
  • PACKAGING SOLUTIONS FOR HIGH BANDWIDTH NETWORKING APPLICATIONS
    Publication number: 20210210478
    Abstract: Embodiments disclosed herein include electronic packages for optical to electrical switching. In an embodiment, an electronic package comprises a first package substrate and a second package substrate attached to the first package substrate. In an embodiment, a die is attached to the second package substrate. In an embodiment, a plurality of photonic engines are attached to a first surface and a second surface of the first package substrate. In an embodiment, the plurality of photonic engines are communicatively coupled to the die through the first package substrate and the second package substrate.
    Type: Application
    Filed: March 3, 2021
    Publication date: July 8, 2021
    Inventors: Susheel JADHAV, Juan DOMINGUEZ, Ankur AGRAWAL, Kenneth BROWN, Yi LI, Jing CHEN, Aditi MALLIK, Xiaoyu HONG, Thomas LILJEBERG, Andrew C. ALDUINO, Ling LIAO, David HUI, Ren-Kang CHIOU, Harinadh POTLURI, Hari MAHALINGAM, Lobna KAMYAB, Sasanka KANUPARTHI, Sushrutha Reddy GUJJULA, Saeed FATHOLOLOUMI, Priyanka DOBRIYAL, Boping XIE, Abiola AWUJOOLA, Vladimir TAMARKIN, Keith MEASE, Stephen KEELE, David SCHWEITZER, Brent ROTHERMEL, Ning TANG, Suresh POTHUKUCHI, Srikant NEKKANTY, Zhichao ZHANG, Kaiyuan ZENG, Baikuan WANG, Donald TRAN, Ravindranath MAHAJAN, Baris BICEN, Grant SMITH
  • Die-stacking using through-silicon vias on bumpless build-up layer substrates including embedded-dice, and processes of forming same
    Patent number: 9406618
    Abstract: An apparatus includes a coreless substrate with a through-silicon via (TSV) embedded die that is integral to the coreless substrate. The apparatus includes a subsequent die that is coupled to the TSV die and that is disposed above the coreless substrate.
    Type: Grant
    Filed: June 16, 2014
    Date of Patent: August 2, 2016
    Assignee: Intel Corporation
    Inventors: John S. Guzek, Ravi K. Nalla, Javier Solo Gonzalez, Drew Delaney, Suresh Pothukuchi, Mohit Mamodia, Edward Zarbock, Johanna M. Swan
  • DIE-STACKING USING THROUGH-SILICON VIAS ON BUMPLESS BUILD-UP LAYER SUBSTRATES INCLUDING EMBEDDED-DICE, AND PROCESSES OF FORMING SAME
    Publication number: 20140327149
    Abstract: An apparatus includes a coreless substrate with a through-silicon via (TSV) embedded die that is integral to the coreless substrate. The apparatus includes a subsequent die that is coupled to the TSV die and that is disposed above the coreless substrate.
    Type: Application
    Filed: July 16, 2014
    Publication date: November 6, 2014
    Inventors: John S. Guzek, Ravi K. Nalla, Javier Solo Gonzalez, Drew Delaney, Suresh Pothukuchi, Mohit Mamodia, Edward Zarbock, Johanna M. Swan
  • DIE-STACKING USING THROUGH-SILICON VIAS ON BUMPLESS BUILD-UP LAYER SUBSTRATES INCLUDING EMBEDDED-DICE, AND PROCESSES OF FORMING SAME
    Publication number: 20140295621
    Abstract: An apparatus includes a coreless substrate with a through-silicon via (TSV) embedded die that is integral to the coreless substrate. The apparatus includes a subsequent die that is coupled to the TSV die and that is disposed above the coreless substrate.
    Type: Application
    Filed: June 16, 2014
    Publication date: October 2, 2014
    Inventors: John S. Guzek, Ravi K. Nalla, Javier Solo Gonzalez, Drew Delaney, Suresh Pothukuchi, Mohit Mamodia, Edward Zarbock, Johanna M. Swan
  • Die-stacking using through-silicon vias on bumpless build-up layer substrates including embedded-dice, and processes of forming same
    Patent number: 8786066
    Abstract: An apparatus includes a coreless substrate with a through-silicon via (TSV) embedded die that is integral to the coreless substrate. The apparatus includes a subsequent die that is coupled to the TSV die and that is disposed above the coreless substrate.
    Type: Grant
    Filed: September 24, 2010
    Date of Patent: July 22, 2014
    Assignee: Intel Corporation
    Inventors: John S. Guzek, Ravi K. Nalla, Javier Soto Gonzalez, Drew Delaney, Suresh Pothukuchi, Mohit Mamodia, Edward Zarbock, Johanna M. Swan
  • DIE-STACKING USING THROUGH-SILICON VIAS ON BUMPLESS BUILD-UP LAYER SUBSTRATES INCLUDING EMBEDDED-DICE, AND PROCESSES OF FORMING SAME
    Publication number: 20120074581
    Abstract: An apparatus includes a coreless substrate with a through-silicon via (TSV) embedded die that is integral to the coreless substrate. The apparatus includes a subsequent die that is coupled to the TSV die and that is disposed above the coreless substrate.
    Type: Application
    Filed: September 24, 2010
    Publication date: March 29, 2012
    Inventors: John S. Guzek, Ravi K. Nalla, Javier Soto Gonzalez, Drew Delaney, Suresh Pothukuchi, Mohit Mamodia, Edward Zarbock, Johanna M. Swan