Patents by Inventor Suresh Potla

Suresh Potla has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Flash memory array structure and method of forming
    Patent number: 6897516
    Abstract: A method of forming a flash memory array structure includes forming a first dielectric layer outwardly from a semiconductor substrate, removing a portion of the first dielectric layer and the substrate to create a trench isolation region, forming a second dielectric layer in the trench isolation region, removing a portion of the second dielectric layer to create an exposed substrate region proximate a bottom of the trench isolation region, doping the exposed substrate region with an n-type dopant, and forming a silicide region in the exposed substrate region.
    Type: Grant
    Filed: April 10, 2003
    Date of Patent: May 24, 2005
    Assignee: Texas Instruments Incorporated
    Inventors: Freidoon Mehrad, Suresh Potla, Zhihao Chen
  • Gate edge diode leakage reduction
    Patent number: 6847089
    Abstract: An embodiment of the invention is an integrated circuit 2 having halo atoms 12 concentrated at a gate side of a channel region and impurity atoms 14 within the channel region. Another embodiment of the invention is a method of manufacturing an integrated circuit that includes the implantation of impurity atoms 14 into a semiconductor substrate 11.
    Type: Grant
    Filed: April 3, 2003
    Date of Patent: January 25, 2005
    Assignee: Texas Instruments Incorporated
    Inventors: Srinivasan Chakravarthi, Suresh Potla, Gordon P. Pollack, Amitabh Jain
  • Gate edge diode leakage reduction
    Publication number: 20040195633
    Abstract: An embodiment of the invention is an integrated circuit 2 having halo atoms 12 concentrated at a gate side of a channel region and impurity atoms 14 within the channel region. Another embodiment of the invention is a method of manufacturing an integrated circuit that includes the implantation of impurity atoms 14 into a semiconductor substrate 11.
    Type: Application
    Filed: April 3, 2003
    Publication date: October 7, 2004
    Inventors: Srinivasan Chakravarthi, Suresh Potla, Gordon P. Pollack, Amitabh Jain
  • Gate edge diode leakage reduction
    Publication number: 20040195631
    Abstract: An embodiment of the invention is an integrated circuit 2 having halo atoms 12 concentrated at a gate side of a channel region and impurity atoms 14 within the channel region. Another embodiment of the invention is a method of manufacturing an integrated circuit that includes the implantation of impurity atoms 14 into a semiconductor substrate 11.
    Type: Application
    Filed: January 12, 2004
    Publication date: October 7, 2004
    Inventors: Srinivasan Chakravarthi, Suresh Potla, Gordon P. Pollack, Amitabh Jain
  • Flash memory array structure and method of forming
    Publication number: 20030207527
    Abstract: A method of forming a flash memory array structure includes forming a first dielectric layer outwardly from a semiconductor substrate, removing a portion of the first dielectric layer and the substrate to create a trench isolation region, forming a second dielectric layer in the trench isolation region, removing a portion of the second dielectric layer to create an exposed substrate region proximate a bottom of the trench isolation region, doping the exposed substrate region with an n-type dopant, and forming a silicide region in the exposed substrate region.
    Type: Application
    Filed: April 10, 2003
    Publication date: November 6, 2003
    Inventors: Freidoon Mehrad, Suresh Potla, Zhihao Chen
  • Flash memory array structure and method of forming
    Patent number: 6566200
    Abstract: A method of forming a flash memory array structure includes forming a first dielectric layer outwardly from a semiconductor substrate, removing a portion of the first dielectric layer and the substrate to create a trench isolation region, forming a second dielectric layer in the trench isolation region, removing a portion of the second dielectric layer to create an exposed substrate region proximate a bottom of the trench isolation region, doping the exposed substrate region with an n-type dopant, and forming a silicide region in the exposed substrate region.
    Type: Grant
    Filed: June 20, 2002
    Date of Patent: May 20, 2003
    Assignee: Texas Instruments Incorporated
    Inventors: Freidoon Mehrad, Suresh Potla, Zhihao Chen
  • Flash memory array structure and method of forming
    Publication number: 20030006448
    Abstract: A method of forming a flash memory array structure includes forming a first dielectric layer outwardly from a semiconductor substrate, removing a portion of the first dielectric layer and the substrate to create a trench isolation region, forming a second dielectric layer in the trench isolation region, removing a portion of the second dielectric layer to create an exposed substrate region proximate a bottom of the trench isolation region, doping the exposed substrate region with an n-type dopant, and forming a silicide region in the exposed substrate region.
    Type: Application
    Filed: June 20, 2002
    Publication date: January 9, 2003
    Inventors: Freidoon Mehrad, Suresh Potla, Zhihao Chen