Abstract: A piezoelectric device comprises: a substrate (12) and a lead magnesium niobate-lead titanate (PMNPT) piezoelectric film on the substrate (12). The PMNPT film comprises: a thermal oxide layer (20) on the substrate (12); a first electrode above on the thermal oxide layer (20); a seed layer (26) above the first electrode; a lead magnesium niobate-lead titanate (PMNPT) piezoelectric layer (16) on the seed layer (26), and a second electrode on the PMNPT piezoelectric layer (16). The PMNPT film comprises a piezoelectric coefficient (d33) of greater than or equal to 200 pm/V.

Abstract: A method of forming a planar surface for a semiconductor device structure. The method comprises forming a particle film comprising a plurality of discrete particles on a non-planar surface of a semiconductor device structure. The semiconductor device structure is subjected to at least one chemical-mechanical polishing process after forming the particle film on the non-planar surface of the semiconductor device structure. Methods of forming a semiconductor device structure are also described.

Abstract: A method of forming a planar surface for a semiconductor device structure. The method comprises forming a particle film comprising a plurality of discrete particles on a non-planar surface of a semiconductor device structure. The semiconductor device structure is subjected to at least one chemical-mechanical polishing process after forming the particle film on the non-planar surface of the semiconductor device structure. Methods of forming a semiconductor device structure are also described.

Abstract: A method of processing a substrate having integrated circuitry includes forming through-substrate vias partially through the substrate from a first side of the substrate. At least one through-substrate structure is formed partially through the substrate from the first substrate side. The at least one through-substrate structure extends deeper into the substrate than do the through-substrate vias. Substrate material is removed from a second side of the substrate to expose the through-substrate vias and the at least one through-substrate structure on the second substrate side. Additional implementations are disclosed. Integrated circuit substrates are disclosed independent of method of manufacture.

Abstract: Some embodiments include methods for quality testing material removal procedures. A test structure is formed to contain a pair of electrically conductive segments. The segments are the same relative to a detectable property as long as they are electrically connected, but becoming different relative to such property if they are disconnected from one another. A material is formed over the test structure, and across a region of a semiconductor substrate proximate to the test structure. The material is subjected to a procedure which removes at least some of it, and which fabricates a structure of an integrated circuit construction in the region proximate to the test structure. After the procedure, it is determined if the segments are the same relative to the detectable property.

Abstract: A system and method for simulating a networked system for testing of embedded software on an emulated hardware device. The system provides for automated generation of a simulated hardware and facilitates testing of embedded software response to simulated error conditions created by the simulated hardware. Communications from the embedded software are intercepted at a low software level and redirected from the emulated hardware device to the simulated hardware.