Patents by Inventor Suresh Subramaniam

Suresh Subramaniam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140276161
    Abstract: An improved method and apparatus for displaying periodic signals generated by a medical device is disclosed.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Applicant: GestlnTime, Inc.
    Inventor: Suresh SUBRAMANIAM
  • Publication number: 20140267358
    Abstract: A method and apparatus for displaying periodic signals generated by a medical device is disclosed. A method and apparatus for displaying quasi-periodic signals generated by a medical device also is disclosed.
    Type: Application
    Filed: June 7, 2013
    Publication date: September 18, 2014
    Inventors: Rohit MITTAL, Krishna Garimella, Suresh Subramaniam
  • Publication number: 20140276126
    Abstract: An improved method and apparatus for providing integrated medical services is disclosed.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Applicant: GestInTime, Inc.
    Inventors: Suresh SUBRAMANIAM, Krishna GARIMELLA
  • Patent number: 8126681
    Abstract: A method for identifying outlier semiconductor devices from a plurality of semiconductor devices includes performing at least one electrical test to obtain electrical test data including at least one test parameter, applying at least a first data transform processing methodology to the electrical test data to generate processed test data, and applying a second data transform processing methodology that is different from the first data transform processing methodology to process the processed test data. The second data transform processing methodology applies an outlier test limit to identify non-outlier devices that comprise semiconductor devices from the semiconductor devices that conform to the outlier test limit and outlier devices that do not conform to the outlier test limit. The semiconductor devices are dispositioned using the outlier identification results. At least one of the data transform processing methodologies can include statistics.
    Type: Grant
    Filed: September 24, 2009
    Date of Patent: February 28, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Amit V Nahar, John M Carulli, Kenneth M Butler, Thomas J Anderson, Suresh Subramaniam
  • Publication number: 20110071782
    Abstract: A method for identifying outlier semiconductor devices from a plurality of semiconductor devices includes performing at least one electrical test to obtain electrical test data including at least one test parameter, applying at least a first data transform processing methodology to the electrical test data to generate processed test data, and applying a second data transform processing methodology that is different from the first data transform processing methodology to process the processed test data. The second data transform processing methodology applies an outlier test limit to identify non-outlier devices that comprise semiconductor devices from the semiconductor devices that conform to the outlier test limit and outlier devices that do not conform to the outlier test limit. The semiconductor devices are dispositioned using the outlier identification results. At least one of the data transform processing methodologies can include statistics.
    Type: Application
    Filed: September 24, 2009
    Publication date: March 24, 2011
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: AMIT V. NAHAR, JOHN M. CARULLI, JR., KENNETH M. BUTLER, THOMAS J. ANDERSON, SURESH SUBRAMANIAM
  • Patent number: 7557605
    Abstract: A system including a plurality of programmable logic blocks, a plurality of special-purpose blocks, and a configurable high-speed mesh interconnect fabric operatively connecting the plurality of programmable logic blocks and the plurality of special-purpose blocks, where the configurable high-speed mesh interconnect fabric is configured to implement a plurality of interconnect pipeline buses spanning across the system.
    Type: Grant
    Filed: September 14, 2007
    Date of Patent: July 7, 2009
    Assignee: Cswitch Corporation
    Inventors: Godfrey P. D'Souza, Douglas Laird, Malcolm J. Wing, Colin N. Murphy, Dana L. How, Robert Yu, Jay B. Patel, Ivo Dobbelaere, Jason Golbus, Suresh Subramaniam, Mukunda Krishnappa, Pohrong R. Chu, Dave Trossen, Kevin James
  • Publication number: 20090072858
    Abstract: A system including a plurality of programmable logic blocks, a plurality of special-purpose blocks, and a configurable high-speed mesh interconnect fabric operatively connecting the plurality of programmable logic blocks and the plurality of special-purpose blocks, where the configurable high-speed mesh interconnect fabric is configured to implement a plurality of interconnect pipeline buses spanning across the system.
    Type: Application
    Filed: September 14, 2007
    Publication date: March 19, 2009
    Applicant: CSWITCH CORPORATION
    Inventors: Godfrey P. D'Souza, Douglas Laird, Malcolm J. Wing, Colin N. Murphy, Dana L. How, Robert Yu, Jay B. Patel, Ivo Dobbelaere, Jason Golbus, Suresh Subramaniam, Mukunda Krishnappa, Pohrong R. Chu, Dave Trossen, Kevin James
  • Publication number: 20090072856
    Abstract: A system including a configurable memory controller, a memory interface, and a configurable high speed communications fabric comprising a plurality of interconnect stations arranged in an array and operable to implement a plurality of pipelined buses, where the configurable memory controller is operably coupled to the configurable high speed communications fabric using a first interconnect station of the plurality of interconnect stations, where the memory interface is operably coupled to the configurable high speed communications fabric using a second interconnect station of the plurality of interconnect stations, where the plurality of interconnect stations are configured to satisfy a timing requirement of the memory interface, and where the configurable memory controller, the memory interface, and the configurable high speed communications fabric are associated with a configurable integrated circuit.
    Type: Application
    Filed: September 14, 2007
    Publication date: March 19, 2009
    Applicant: Cswitch Corporation
    Inventors: Suresh Subramaniam, Mukunda Krishnappa, Pohrong R. Chu, Jason Golbus, Dana L. How
  • Patent number: 7494829
    Abstract: Systems and methods for identification of outlier semiconductor devices using data-driven statistical characterization are described herein.
    Type: Grant
    Filed: September 28, 2007
    Date of Patent: February 24, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Suresh Subramaniam, Amit Vijay Nahar, Thomas John Anderson, Kenneth Michael Butler, John Michael Carulli
  • Publication number: 20080262793
    Abstract: Systems and methods for identification of outlier semiconductor devices using data-driven statistical characterization are described herein.
    Type: Application
    Filed: September 28, 2007
    Publication date: October 23, 2008
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Suresh SUBRAMANIAM, Amit Vijay NAHAR, Thomas John ANDERSON, Kenneth Michael BUTLER, John Michael CARULLI
  • Patent number: 7129735
    Abstract: A method for test data-driven detection of outlier semiconductor devices. Some illustrative embodiments may be a method used to test a semiconductor die comprising performing a burn-in test of a plurality of sample semiconductor dies to identify a failure of a defective semiconductor die, correlating variations in a parameter with the failure (the parameter comprising a characteristic associated with the plurality of sample semiconductor dies), defining a parameter constraint associated with the parameter, performing a production test of a production semiconductor die, and identifying the production semiconductor die as an outlier semiconductor die (the outlier semiconductor die passing the production test, but failing to conform to the parameter constraint).
    Type: Grant
    Filed: September 10, 2004
    Date of Patent: October 31, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Suresh Subramaniam, Kenneth M. Butler, John M. Carulli, Richard A. Lawrence
  • Publication number: 20060028229
    Abstract: A method for test data-driven detection of outlier semiconductor devices. Some illustrative embodiments may be a method used to test a semiconductor die comprising performing a burn-in test of a plurality of sample semiconductor dies to identify a failure of a defective semiconductor die, correlating variations in a parameter with the failure (the parameter comprising a characteristic associated with the plurality of sample semiconductor dies), defining a parameter constraint associated with the parameter, performing a production test of a production semiconductor die, and identifying the production semiconductor die as an outlier semiconductor die (the outlier semiconductor die passing the production test, but failing to conform to the parameter constraint).
    Type: Application
    Filed: September 10, 2004
    Publication date: February 9, 2006
    Applicant: Texas Instruments Incorporated
    Inventors: Suresh Subramaniam, Kenneth Butler, John Carulli, Richard Lawrence
  • Patent number: 6538777
    Abstract: A method of allocating channels and paths to connections along candidate channel-paths in a network, where a candidate channel-path comprises a candidate path and candidate channel along the candidate path, is performed by determining individual effects, on the network, of selecting candidate channel-paths. These include effects on at least one channel-path, other than a candidate channel-path, which shares links with the candidate path. Candidate channel-paths are selected based on the determined effects and allocated. In a preferred embodiment, determination of the effects on the network is based on path capacity. The embodiment can be used where a single connection has been requested, or alternatively, where multiple connections have been requested.
    Type: Grant
    Filed: October 29, 1998
    Date of Patent: March 25, 2003
    Assignee: Massachusetts Institute of Technology
    Inventors: Richard A. Barry, Suresh Subramaniam