Patents by Inventor Suresh VISHWANATH
Suresh VISHWANATH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240014268Abstract: Integrated circuit structures having source or drain structures with abrupt dopant profiles are described. In an example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires. A second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires. The first and second epitaxial source or drain structures include silicon, phosphorous and arsenic, with an atomic concentration of phosphorous substantially the same as an atomic concentration of arsenic.Type: ApplicationFiled: September 20, 2023Publication date: January 11, 2024Inventors: Ryan KEECH, Anand S. MURTHY, Nicholas G. MINUTILLO, Suresh VISHWANATH, Mohammad HASAN, Biswajeet GUHA, Subrina RAFIQUE
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Patent number: 11804523Abstract: Integrated circuit structures having source or drain structures with abrupt dopant profiles are described. In an example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires. A second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires. The first and second epitaxial source or drain structures include silicon, phosphorous and arsenic, with an atomic concentration of phosphorous substantially the same as an atomic concentration of arsenic.Type: GrantFiled: September 24, 2019Date of Patent: October 31, 2023Assignee: Intel CorporationInventors: Ryan Keech, Anand S. Murthy, Nicholas G. Minutillo, Suresh Vishwanath, Mohammad Hasan, Biswajeet Guha, Subrina Rafique
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Publication number: 20230197785Abstract: Integrated circuit structures having source or drain structures with low resistivity are described. In an example, integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. A gate stack is over the upper fin portion of the fin, the gate stack having a first side opposite a second side. A first source or drain structure includes an epitaxial structure embedded in the fin at the first side of the gate stack. A second source or drain structure includes an epitaxial structure embedded in the fin at the second side of the gate stack. Each epitaxial structure of the first and second source or drain structures include silicon, germanium and boron. The first and second source or drain structures have a resistivity less than or equal to 0.3 mOhm·cm.Type: ApplicationFiled: February 15, 2023Publication date: June 22, 2023Inventors: Cory BOMBERGER, Anand MURTHY, Suresh VISHWANATH
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Publication number: 20230197840Abstract: In one embodiment, a transistor includes a substrate, a buffer layer on the substrate a channel layer on the buffer layer, and one or more polarization layers on the channel layer. The one or more polarization layers include a group III-N material comprising a first group III constituent and a second group III constituent. The transistor further includes a plurality of p-type doped layers on the one or more polarization layers. Each of the plurality of p-type doped layers includes a first p-type dopant and the III-N material, wherein each successive layer of the first p-type doped layers has a lower proportion of the first group III constituent to the second group III constituent relative to a layer below it. The transistor also includes a p-type doped layer on the plurality of p-type doped layers comprising a second p-type dopant and a group III-N material.Type: ApplicationFiled: December 21, 2021Publication date: June 22, 2023Applicant: Intel CorporationInventors: Sanyam Bajaj, Michael S. Beumer, Robert Ehlert, Gregory P. McNerney, Nicholas Minutillo, Xiaoye Qin, Johann C. Rode, Atsunori Tanaka, Suresh Vishwanath, Patrick M. Wallace
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Publication number: 20230132548Abstract: In one embodiment, a transistor is formed by a process comprising forming a buffer layer on a substrate, the buffer layer comprising a first group III-nitride (III-N) material (e.g., AlGaN), forming a channel layer on the buffer layer, the channel layer comprising a second III-N material (e.g., GaN), forming a polarization layer on the channel layer, the polarization layer comprising a third III-N material (e.g., AlGaN), flowing a p-type dopant precursor compound (e.g., Cp2Mg) after forming the polarization layer, forming a p-type doped layer (e.g., p-GaN) on the polarization layer, the p-type doped layer comprising a p-type dopant (e.g., Mg) and a fourth III-N material (e.g., GaN), forming a source region adjacent one end of the channel layer, and forming a drain region adjacent another end of the channel layer.Type: ApplicationFiled: November 4, 2021Publication date: May 4, 2023Applicant: Intel CorporationInventors: Atsunori Tanaka, Sanyam Bajaj, Michael S. Beumer, Robert Ehlert, Gregory P. McNerney, Nicholas Minutillo, Johann C. Rode, Suresh Vishwanath, Patrick M. Wallace
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Patent number: 11621325Abstract: Integrated circuit structures having source or drain structures with low resistivity are described. In an example, integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. A gate stack is over the upper fin portion of the fin, the gate stack having a first side opposite a second side. A first source or drain structure includes an epitaxial structure embedded in the fin at the first side of the gate stack. A second source or drain structure includes an epitaxial structure embedded in the fin at the second side of the gate stack. Each epitaxial structure of the first and second source or drain structures include silicon, germanium and boron. The first and second source or drain structures have a resistivity less than or equal to 0.3 mOhm·cm.Type: GrantFiled: March 28, 2019Date of Patent: April 4, 2023Assignee: Intel CorporationInventors: Cory Bomberger, Anand Murthy, Suresh Vishwanath
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Patent number: 11552169Abstract: Integrated circuit structures having source or drain structures with phosphorous and arsenic co-dopants are described. In an example, an integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. A gate stack is over the upper fin portion of the fin, the gate stack having a first side opposite a second side. A first source or drain structure includes an epitaxial structure embedded in the fin at the first side of the gate stack. A second source or drain structure includes an epitaxial structure embedded in the fin at the second side of the gate stack. The first and second source or drain structures include silicon, phosphorous and arsenic, with an atomic concentration of phosphorous substantially the same as an atomic concentration of arsenic.Type: GrantFiled: March 27, 2019Date of Patent: January 10, 2023Assignee: Intel CorporationInventors: Anand Murthy, Ryan Keech, Nicholas G. Minutillo, Suresh Vishwanath
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Publication number: 20220199615Abstract: Substrate-less vertical diode integrated circuit structures, and methods of fabricating substrate-less vertical diode integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a semiconductor fin in a dielectric layer, the semiconductor fin having a top and a bottom, and the dielectric layer having a top surface and a bottom surface. A first epitaxial semiconductor structure is on the top of the semiconductor fin. A second epitaxial semiconductor structure is on the bottom of the semiconductor fin. A first conductive contact is on the first epitaxial semiconductor structure. A second conductive contact is on the second epitaxial semiconductor structure.Type: ApplicationFiled: December 23, 2020Publication date: June 23, 2022Inventors: Avyaya JAYANTHINARASIMHAM, Brian GREENE, Suresh Vishwanath
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Publication number: 20210407851Abstract: Integrated circuit structures having source or drain structures with a high germanium concentration capping layer are described. In an example, an integrated circuit structure includes source or drain structures including an epitaxial structure embedded in a fin at a side of a gate stack. The epitaxial structure has a lower semiconductor layer and a capping semiconductor layer on the lower semiconductor layer with an abrupt interface between the capping semiconductor layer and the lower semiconductor layer. The lower semiconductor layer includes silicon, germanium and boron, the germanium having an atomic concentration of less than 40% at the abrupt interface. The capping semiconductor layer includes silicon, germanium and boron, the germanium having an atomic concentration of greater than 50% at the abrupt interface and throughout the capping semiconductor layer.Type: ApplicationFiled: June 26, 2020Publication date: December 30, 2021Inventors: Cory BOMBERGER, Suresh VISHWANATH, Yulia TOLSTOVA, Pratik PATEL, Szuya S. LIAO, Anand S. MURTHY
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Publication number: 20210408275Abstract: Integrated circuit structures having high surface germanium concentrations are described. In an example, an integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. A gate stack is over the upper fin portion of the fin, the gate stack having a first side opposite a second side. A first source or drain structure has an epitaxial structure embedded in the fin at the first side of the gate stack. A second source or drain structure has an epitaxial structure embedded in the fin at the second side of the gate stack. Each of the epitaxial structures of the first and second source or drain structures includes silicon, germanium and boron, the germanium having an atomic concentration of greater than 55% at a top surface of each of the epitaxial structures of the first and second source or drain structures.Type: ApplicationFiled: June 26, 2020Publication date: December 30, 2021Inventors: Cory BOMBERGER, Suresh VISHWANATH, Pratik PATEL, Szuya S. LIAO, Anand S. MURTHY
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Publication number: 20210408258Abstract: Approaches for fabricating an integrated circuit structure including a titanium silicide material, and the resulting structures, are described. In an example, an integrated circuit structure includes a semiconductor fin above a substrate, a gate electrode over the top and adjacent to the sidewalls of a portion of the semiconductor fin. A titanium silicide material is in direct contact with each of first and second epitaxial semiconductor source or drain structures at first and second sides of the gate electrode. The titanium silicide material is conformal with and hermetically sealing a non-flat topography of each of the first and second epitaxial semiconductor source or drain structures. The titanium silicide material has a total atomic composition including 95% or greater stoichiometric TiSi2.Type: ApplicationFiled: June 25, 2020Publication date: December 30, 2021Inventors: Dan S. LAVRIC, Glenn A. GLASS, Thomas T. TROEGER, Suresh VISHWANATH, Jitendra Kumar JHA, John F. RICHARDS, Anand S. MURTHY, Srijit MUKHERJEE
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Publication number: 20210399119Abstract: Embodiments disclosed herein comprise a high electron mobility transistor (HEMT). In an embodiment, the HEMT comprises a heterojunction channel that includes a first semiconductor layer and a second semiconductor layer over the first semiconductor layer. In an embodiment a first interface layer is between the first semiconductor layer and the second semiconductor layer, and a second interface layer is over the first interface layer. In an embodiment, the HEMT further comprises a source contact, a drain contact, and a gate contact between the source contact and the drain contact.Type: ApplicationFiled: June 23, 2020Publication date: December 23, 2021Inventors: Suresh VISHWANATH, Roza KOTLYAR, Han Wui THEN, Robert EHLERT, Glenn A. GLASS, Anand S. MURTHY, Sandrine CHARUE-BAKKER
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Publication number: 20210091181Abstract: Integrated circuit structures having source or drain structures with abrupt dopant profiles are described. In an example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires. A second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires. The first and second epitaxial source or drain structures include silicon, phosphorous and arsenic, with an atomic concentration of phosphorous substantially the same as an atomic concentration of arsenic.Type: ApplicationFiled: September 24, 2019Publication date: March 25, 2021Inventors: Ryan KEECH, Anand S. MURTHY, Nicholas G. MINUTILLO, Suresh VISHWANATH, Mohammad HASAN, Biswajeet GUHA, Subrina RAFIQUE
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Publication number: 20200312958Abstract: Integrated circuit structures having source or drain structures with phosphorous and arsenic co-dopants are described. In an example, an integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. A gate stack is over the upper fin portion of the fin, the gate stack having a first side opposite a second side. A first source or drain structure includes an epitaxial structure embedded in the fin at the first side of the gate stack. A second source or drain structure includes an epitaxial structure embedded in the fin at the second side of the gate stack. The first and second source or drain structures include silicon, phosphorous and arsenic, with an atomic concentration of phosphorous substantially the same as an atomic concentration of arsenic.Type: ApplicationFiled: March 27, 2019Publication date: October 1, 2020Inventors: Anand MURTHY, Ryan KEECH, Nicholas G. MINUTILLO, Suresh VISHWANATH
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Publication number: 20200312959Abstract: Integrated circuit structures having source or drain structures with low resistivity are described. In an example, integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. A gate stack is over the upper fin portion of the fin, the gate stack having a first side opposite a second side. A first source or drain structure includes an epitaxial structure embedded in the fin at the first side of the gate stack. A second source or drain structure includes an epitaxial structure embedded in the fin at the second side of the gate stack. Each epitaxial structure of the first and second source or drain structures include silicon, germanium and boron. The first and second source or drain structures have a resistivity less than or equal to 0.3 mOhm·cm.Type: ApplicationFiled: March 28, 2019Publication date: October 1, 2020Inventors: Cory BOMBERGER, Anand MURTHY, Suresh VISHWANATH
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Patent number: 9357263Abstract: Guide acquisition method and apparatus for receiving a satellite broadcast stream containing guide data, encapsulating said broadcast stream containing guide data in a network communication protocol, assigning a multicast address to said broadcast stream containing guide data, transmitting said broadcast stream containing guide data, receiving a request for said guide data wherein said request comprises a satellite network identifier and transmitting a said multicast address in response to said request.Type: GrantFiled: December 17, 2012Date of Patent: May 31, 2016Assignee: Thomson LicensingInventors: Suresh Vishwanath Leley, Thomas Anthony Stahl
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Publication number: 20140351859Abstract: Guide acquisition method and apparatus for receiving a satellite broadcast stream containing guide data, encapsulating said broadcast stream containing guide data in a network communication protocol, assigning a multicast address to said broadcast stream containing guide data, transmitting said broadcast stream containing guide data, receiving a request for said guide data wherein said request comprises a satellite network identifier and transmitting a said multicast address in response to said request.Type: ApplicationFiled: December 17, 2012Publication date: November 27, 2014Inventors: Suresh Vishwanath Leley, Thomas Anthony Stahl
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Patent number: 6442255Abstract: A subscriber callback modem, includes a source of callback data. A modem is coupled to a subscriber telephone line, and a control circuit is coupled between the data source and the modem, for conditioning the modem to automatically call a central computer and transfer the callback data from the data source to the central computer.Type: GrantFiled: June 16, 1998Date of Patent: August 27, 2002Assignee: Thomson Licensing S.A.Inventors: Robert Alan Pitsch, Suresh Vishwanath Leley, Michael Gene Kelly