Abstract: Described examples include an integrated circuit having an input stage with an input and an output. A first current mirror is coupled to the output, the first current mirror including a first transistor having an emitter and a base coupled to the output of the input stage, and a collector coupled to a reference potential. The first current mirror also includes a second transistor having a base coupled to the base of the first transistor, an emitter coupled to the reference potential and a collector coupled to an output node. A buffer has an input coupled to the output node and an output. A third transistor has a base and an emitter coupled to the reference potential and a collector coupled to the output of the buffer. A second current mirror couples a portion of the buffer output current to the base of the first transistor.

Abstract: Described examples include an integrated circuit having an input stage with an input and an output. A first current mirror is coupled to the output, the first current mirror including a first transistor having an emitter and a base coupled to the output of the input stage, and a collector coupled to a reference potential. The first current mirror also includes a second transistor having a base coupled to the base of the first transistor, an emitter coupled to the reference potential and a collector coupled to an output node. A buffer has an input coupled to the output node and an output. A third transistor has a base and an emitter coupled to the reference potential and a collector coupled to the output of the buffer. A second current mirror couples a portion of the buffer output current to the base of the first transistor.

Abstract: A buffer circuit includes a first PNP BJT having a first base, a first collector and a first emitter. A first diode has a first cathode and a first anode. The first cathode couples to the first PNP BJT. A second diode has a second cathode and a second anode. The second anode couple to first base, and the second cathode couples to the first emitter. A voltage level shifter circuit coupled to the first anode. The voltage level shifter has a voltage level shifter output. A pre-driver circuit has a pre-driver input coupled to the voltage level shifter output. A second transistor has a second base, a second collector and a second emitter. The second base couples to the output of the pre-driver output. The second collector couples to a negative supply voltage node. The second emitter couples to an output node of the buffer circuit.

Abstract: A buffer circuit includes a first PNP BJT having a first base, a first collector and a first emitter. A first diode has a first cathode and a first anode. The first cathode couples to the first PNP BJT. A second diode has a second cathode and a second anode. The second anode couple to first base, and the second cathode couples to the first emitter. A voltage level shifter circuit coupled to the first anode. The voltage level shifter has a voltage level shifter output. A pre-driver circuit has a pre-driver input coupled to the voltage level shifter output. A second transistor has a second base, a second collector and a second emitter. The second base couples to the output of the pre-driver output. The second collector couples to a negative supply voltage node. The second emitter couples to an output node of the buffer circuit.

Abstract: A circuit for slew rate control for a high-side switch is disclosed. The circuit comprises a sample and level-shift circuit. The sample and level-shift circuit is connected to the high-side switch. The circuit further comprises a sampling capacitor, and the sampling capacitor is configured to sample an input voltage corresponding to the sample and level-shift circuit. Additionally, the circuit includes a charge-limiting circuit. The sampling capacitor is configured to charge a gate capacitance of the high-side switch. The charge-limiting circuit is configured to limit a rate of charge transferred to the gate capacitance of the high-side switch per unit of time.

Abstract: A gate driver circuit for driving a high-side switch is disclosed. The gate driver circuit comprises a sample and level-shift circuit. The sample and level-shift circuit is connected to the high-side switch. The gate driver circuit further comprises a sampling capacitor. The sampling capacitor is configured to sample an output voltage of an at least one amplifier. The gate driver circuit additionally includes at least one voltage supply. The at least one voltage supply is connected to the at least one amplifier. The sampling capacitor is configured to charge a gate capacitance of the high-side switch, and the at least one amplifier is configured to limit a high-side switch output current.

Abstract: A gate driver circuit for driving a high-side switch is disclosed. The gate driver circuit comprises a sample and level-shift circuit. The sample and level-shift circuit is connected to the high-side switch. The gate driver circuit further comprises a sampling capacitor. The sampling capacitor is configured to sample an output voltage of an at least one amplifier. The gate driver circuit additionally includes at least one voltage supply. The at least one voltage supply is connected to the at least one amplifier. The sampling capacitor is configured to charge a gate capacitance of the high-side switch, and the at least one amplifier is configured to limit a high-side switch output current.

Abstract: A circuit for slew rate control for a high-side switch is disclosed. The circuit comprises a sample and level-shift circuit. The sample and level-shift circuit is connected to the high-side switch. The circuit further comprises a sampling capacitor, and the sampling capacitor is configured to sample an input voltage corresponding to the sample and level-shift circuit. Additionally, the circuit includes a charge-limiting circuit. The sampling capacitor is configured to charge a gate capacitance of the high-side switch. The charge-limiting circuit is configured to limit a rate of charge transferred to the gate capacitance of the high-side switch per unit of time.

Abstract: In one embodiment, an apparatus for performing power factor correction is provided. A power factor corrector includes an input configured to sense a current from an input circuit. A reference generator generates a current limit based on an input voltage. The current limit reference is dynamically changed based on the input voltage. A control signal generator controls the current in the input circuit based on a comparison of the current and the generated current limit.

Abstract: In one embodiment, an apparatus for performing power factor correction is provided. A power factor corrector includes an input configured to sense a current from an input circuit. A reference generator generates a current limit based on an input voltage. The current limit reference is dynamically changed based on the input voltage. A control signal generator controls the current in the input circuit based on a comparison of the current and the generated current limit.