Patents by Inventor Surinder Kumar
Surinder Kumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 12511131Abstract: Techniques for optimized aggregation of a data source are described. A server device receives a request from a data source for aggregating thereof and compares each of a set of hardware metrics corresponding to hardware configuration of the server device with a corresponding threshold hardware metric. The server device is classified as a small-configuration device or a high-configuration device and complete aggregation of the data source or partial aggregation of the data source is allowed based on the classification. A set of utilized hardware metrics of the server device that corresponds to hardware resources of the server device that is being utilized is determined. One or more operations corresponding to the transmission of data of the data source that is to be performed by the server device is blocked if at least one of the set of utilized hardware metrics is higher than a corresponding threshold operational soft limit.Type: GrantFiled: October 13, 2023Date of Patent: December 30, 2025Assignee: HONEYWELL INTERNATIONAL INC.Inventors: Surinder Kumar, Rod Stein, Sivasankari Shanmugham
-
Publication number: 20250276953Abstract: This invention is in the field of medicinal chemistry. In particular, the invention relates to a new class of small-molecules having a 2-hydroxybenzoic acid structure which function as sirtuin (e.g., SIRT1, SIRT2, SIRT3, SIRT4, SIRT5, SIRT6, SIRT7) inhibitors and/or degraders which function as effective therapeutic agents for treating, ameliorating, and preventing disorders associated with sirtuin activity (e.g., melanoma, Ewing sarcoma, malignant peripheral nerve sheath tumor, non-small cell lung cancer). In addition, this invention also relates to a new class of proteolysis-targeting chimeras (PROTACs) (as defined herein) which function as sirtuin inhibitors and/or degraders within cancer and/or immune cells. Pharmaceutical compositions comprising said compounds are also within the scope of the present invention.Type: ApplicationFiled: April 28, 2023Publication date: September 4, 2025Inventors: Nouri Neamati, Yanghan Liu, Surinder Kumar, David B. Lombard
-
Publication number: 20250141976Abstract: Examples techniques of data provisioning in an industrial facility are described. A first data broker receives from a client, a request for data from a data source. A second data broker samples the data from the data source at a sampling interval specified in the request and publishes the sampled data to an upstream data broker at publishing interval specified in the request. The upstream data broker is an intermediate data broker positioned between the first data broker and the second data broker in a hierarchical chain data brokers implemented in a communication network of the 10 industrial facility. The intermediate data broker configured to receive the published data and transmit the received data to the first data broker at a sampling and publishing intervals less than the second data broker.Type: ApplicationFiled: November 6, 2024Publication date: May 1, 2025Inventors: Rod Stein, Surinder Kumar
-
Publication number: 20250123849Abstract: Techniques for optimized aggregation of a data source are described. A server device receives a request from a data source for aggregating thereof and compares each of a set of hardware metrics corresponding to hardware configuration of the server device with a corresponding threshold hardware metric. The server device is classified as a small-configuration device or a high-configuration device and complete aggregation of the data source or partial aggregation of the data source is allowed based on the classification. A set of utilized hardware metrics of the server device that corresponds to hardware resources of the server device that is being utilized is determined. One or more operations corresponding to the transmission of data of the data source that is to be performed by the server device is blocked if at least one of the set of utilized hardware metrics is higher than a corresponding threshold operational soft limit.Type: ApplicationFiled: October 13, 2023Publication date: April 17, 2025Inventors: Surinder Kumar, Rod Stein, Sivasankari Shanmugham
-
Patent number: 8930395Abstract: A computer system monitors database servers to mitigate server availability risks. The plurality of servers may be proactively monitored to determine database status at each server before an alert is generated. An automated proactive process executes at a user's desktop to monitor database features over a plurality of database servers. Information about the server status is presented in a graphical user interface (GUI) format where status information for all of the database servers is presented in one integrated view in an automated manner. For example, the monitoring process reads a list of SQL instances and then connects to each listed SQL server to query the system catalogs of an SQL server engine. The monitoring process interprets the received information from the SQL servers and updates the GUI. The GUI may be color-coded to indicate the status state of individual SQL features for each monitored SQL server.Type: GrantFiled: January 10, 2012Date of Patent: January 6, 2015Assignee: Bank of America CorporationInventors: Anant Bondalapati Sharma, Deepak Ranjan Mishra, Surinder Kumar
-
Publication number: 20130179461Abstract: A computer system monitors database servers to mitigate server availability risks. The plurality of servers may be proactively monitored to determine database status at each server before an alert is generated. An automated proactive process executes at a user's desktop to monitor database features over a plurality of database servers. Information about the server status is presented in a graphical user interface (GUI) format where status information for all of the database servers is presented in one integrated view in an automated manner. For example, the monitoring process reads a list of SQL instances and then connects to each listed SQL server to query the system catalogs of an SQL server engine. The monitoring process interprets the received information from the SQL servers and updates the GUI. The GUI may be color-coded to indicate the status state of individual SQL features for each monitored SQL server.Type: ApplicationFiled: January 10, 2012Publication date: July 11, 2013Applicant: Bank of AmericaInventors: Anant Bondalapati Sharma, Deepak Ranjan Mishra, Surinder Kumar
-
Patent number: 7760031Abstract: A method is provided for reducing inter modulation distortion products using multi-carrier phase alignment of the type where a combined carrier signal is generated from the combined output carried waves of a plurality of numerically controlled oscillators in which the frequency of the carrier wave can be altered by changing an input value into the oscillator. In particular the initial phase of the output carrier waves is adjusted so that the peak amplitude of the combined carrier signal is minimized so that compression of the higher amplitude portions of the combined signal is reduced.Type: GrantFiled: March 7, 2008Date of Patent: July 20, 2010Assignee: Vecima Networks Inc.Inventors: Gregory Clayton Whittet, Surinder Kumar
-
Patent number: 7492832Abstract: Direct digital QAM modulation at an RF frequency is obtained from digitally synthesized RF signals which are generated for use as the two vectors. The two vectors are individually controlled in phase and summed to provide a combined phase and amplitude modulation that forms the modulated signal. The synthesized RF signal is generated from a higher reference frequency using a variable pulse stretching technique implemented with programmable delay lines. The amount of the pulse stretch in each cycle is controlled by a phase increment value. Pulse stretching can be extended beyond one cycle by pulse swallowing, allowing the generation of an RF signal from DC up to and including the input reference frequency. Phase modulation is added by digital control of the pulse stretching according to the phase modulation data bits.Type: GrantFiled: March 10, 2004Date of Patent: February 17, 2009Assignee: Vecima Networks Inc.Inventors: Gerald Harron, Surinder Kumar
-
Publication number: 20080224784Abstract: A method is provided for reducing inter modulation distortion products using multi-carrier phase alignment of the type where a combined carrier signal is generated from the combined output carried waves of a plurality of numerically controlled oscillators in which the frequency of the carrier wave can be altered by changing an input value into the oscillator. In particular the initial phase of the output carrier waves is adjusted so that the peak amplitude of the combined carrier signal is minimized so that compression of the higher amplitude portions of the combined signal is reduced.Type: ApplicationFiled: March 7, 2008Publication date: September 18, 2008Inventors: Gregory Clayton Whittet, Surinder Kumar
-
Patent number: 7383296Abstract: A method to improve the frequency resolution and phase noise of a synthesized RF signal results in superior instantaneous frequency change and phase modulation capability, wide frequency set ability, and suitability for implementation in a digital ASIC. The RF signal synthesis is achieved from a higher reference frequency clock signal using a variable pulse stretching technique. The amount of the pulse stretch in each cycle is set by a phase increment value and is implemented using programmable delay lines. Pulse stretching can be extended beyond one cycle by pulse swallowing, allowing the generation of an RF signal with frequencies from DC up to the input reference frequency. Phase modulation is incorporated by digital control of the phase stretching with the phase modulation bits.Type: GrantFiled: March 10, 2004Date of Patent: June 3, 2008Assignee: Vecima Networks Inc.Inventors: Gerald Harron, Surinder Kumar
-
Patent number: 7248664Abstract: A time-sliced discrete-time Phase Locked Loop which is suitable for simultaneously synchronizing multiple input signals to multiple output signals is provided by implementing a discrete-time phase detector, loop filter, and voltage controlled oscillator that together operate as a single discrete-time PLL in hardware and applying control logic to retrieve the history for each signal pair from a context memory (RAM), to enable the discrete-time PLL hardware, and to store the resulting history in the context memory for use in subsequent operations for a particular input/output signal pair.Type: GrantFiled: September 29, 2003Date of Patent: July 24, 2007Assignee: Vecima Networks Inc.Inventors: Douglas Fast, Surinder Kumar, Sumit Kumar
-
Patent number: 7084676Abstract: The present invention provides a method to improve the frequency resolution and phase noise of a synthesized RF signal. It also results in the superior characteristics of instantaneous frequency changeability, wide frequency setting ability, and fully digital ASIC implementation ability. The synthesized RF signal is generated from a higher reference frequency using a variable pulse stretching technique. The amount of the pulse stretch in each cycle is controlled by a phase increment value and is implemented using programmable delay lines. Pulse stretching is extended beyond one cycle by pulse swallowing, allowing the generation of an RF signal from DC up to the input reference clock signal frequency.Type: GrantFiled: March 10, 2004Date of Patent: August 1, 2006Assignee: VCom Inc.Inventors: Gerald Harron, Surinder Kumar
-
Patent number: 7012477Abstract: The present invention provides a means to implement amplitude and phase modulation digitally and directly at an RF frequency that benefits from high output power without the use of amplifiers. This is accomplished by the combination of two varying amplitude and phase vectors. A reference oscillator produces a carrier signal, which is supplied to two digital delay lines composed of a sequence of delay banks. The delay lines are controlled by lookup tables that are updated by the vector control circuit, used to determine the delay of each digital delay line. The output of each delay line is multiplexed to a switching bank which is also controlled by the vector control circuit. The output of the switching bank, in combination with a summer, is used to produce discrete amplitude adjustment of the vector.Type: GrantFiled: March 10, 2004Date of Patent: March 14, 2006Assignee: VCom Inc.Inventors: Gerald Harron, Jason T. Tucker, Surinder Kumar
-
Patent number: 6982607Abstract: The present invention provides a means to implement amplitude and phase modulation digitally and directly at an RF frequency that benefits from high output power using non-linear amplifiers. This is accomplished by the combination of two constant amplitude phase varying vectors. A reference oscillator produces a carrier signal, which is supplied to two digital delay lines composed of a sequence of delay banks. The delay lines are controlled by lookup tables that are updated by the vector control circuit used to determine the delay of each digital delay line. The delay of the lines are set in such a way as to produce two vectors with the desired phase shift that, when summed together, produce a vector with the desired phase and amplitude characteristics.Type: GrantFiled: March 10, 2004Date of Patent: January 3, 2006Assignee: VCom Inc.Inventors: Gerald Harron, Jason T. Tucker, Surinder Kumar
-
Publication number: 20050116785Abstract: The present invention provides a means to implement amplitude and phase modulation digitally and directly at an RF frequency that benefits from high output power without the use of amplifiers. This is accomplished by the combination of two varying amplitude and phase vectors. A reference oscillator produces a carrier signal, which is supplied to two digital delay lines composed of a sequence of delay banks. The delay lines are controlled by lookup tables that are updated by the vector control circuit, used to determine the delay of each digital delay line. The output of each delay line is multiplexed to a switching bank which is also controlled by the vector control circuit. The output of the switching bank, in combination with a summer, is used to produce discrete amplitude adjustment of the vector.Type: ApplicationFiled: March 10, 2004Publication date: June 2, 2005Inventors: Gerald Harron, Jason Tucker, Surinder Kumar
-
Publication number: 20050116786Abstract: The present invention provides a means to implement amplitude and phase modulation digitally and directly at an RF frequency that benefits from high output power using non-linear amplifiers. This is accomplished by the combination of two constant amplitude phase varying vectors. A reference oscillator produces a carrier signal, which is supplied to two digital delay lines composed of a sequence of delay banks. The delay lines are controlled by lookup tables that are updated by the vector control circuit used to determine the delay of each digital delay line. The delay of the lines are set in such a way as to produce two vectors with the desired phase shift that, when summed together, produce a vector with the desired phase and amplitude characteristics.Type: ApplicationFiled: March 10, 2004Publication date: June 2, 2005Inventors: Gerald Harron, Jason Tucker, Surinder Kumar
-
Publication number: 20050089117Abstract: A method to implement direct digital QAM modulation at an RF frequency results in the superior characteristics of high output power using non-linear amplifiers, high frequency resolution, low phase noise, instantaneous frequency change capability, wide frequency setting ability, and suitability for full implementation in a digital ASIC. Two digitally synthesized RF signals are generated for use as the two vectors. The two vectors are individually controlled in phase and summed to provide a combined phase and amplitude modulation that forms the modulated signal. The synthesized RF signal is generated from a higher reference frequency using a variable pulse stretching technique implemented with programmable delay lines. The amount of the pulse stretch in each cycle is controlled by a phase increment value. Pulse stretching can be extended beyond one cycle by pulse swallowing, allowing the generation of an RF signal from DC up to and including the input reference frequency.Type: ApplicationFiled: March 10, 2004Publication date: April 28, 2005Inventors: Gerald Harron, Surinder Kumar
-
Publication number: 20050091295Abstract: A method to improve the frequency resolution and phase noise of a synthesized RF signal results in superior instantaneous frequency change and phase modulation capability, wide frequency set ability, and suitability for implementation in a digital ASIC. The RF signal synthesis is achieved from a higher reference frequency clock signal using a variable pulse stretching technique. The amount of the pulse stretch in each cycle is set by a phase increment value and is implemented using programmable delay lines. Pulse stretching can be extended beyond one cycle by pulse swallowing, allowing the generation of an RF signal with frequencies from DC up to the input reference frequency. Phase modulation is incorporated by digital control of the phase stretching with the phase modulation bits.Type: ApplicationFiled: March 10, 2004Publication date: April 28, 2005Inventors: Gerald Harron, Surinder Kumar
-
Publication number: 20050083085Abstract: The present invention provides a method to improve the frequency resolution and phase noise of a synthesized RF signal. It also results in the superior characteristics of instantaneous frequency changeability, wide frequency setting ability, and fully digital ASIC implementation ability. The synthesized RF signal is generated from a higher reference frequency using a variable pulse stretching technique. The amount of the pulse stretch in each cycle is controlled by a phase increment value and is implemented using programmable delay lines. Pulse stretching is extended beyond one cycle by pulse swallowing, allowing the generation of an RF signal from DC up to the input reference clock signal frequency.Type: ApplicationFiled: March 10, 2004Publication date: April 21, 2005Inventors: Gerald Harron, Surinder Kumar
-
Publication number: 20040131136Abstract: A time-sliced discrete-time Phase Locked Loop which is suitable for simultaneously synchronizing multiple input signals to multiple output signals is provided by implementing a discrete-time phase detector, loop filter, and voltage controlled oscillator that together operate as a single discrete-time PLL in hardware and applying control logic to retrieve the history for each signal pair from a context memory (RAM), to enable the discrete-time PLL hardware, and to store the resulting history in the context memory for use in subsequent operations for a particular input/output signal pair.Type: ApplicationFiled: September 29, 2003Publication date: July 8, 2004Inventors: Douglas Fast, Surinder Kumar, Sumit Kumar