Abstract: In a computer-implemented method for improving a k-means clustering algorithm, a processor modifies a first data point of a data set to include a first distribution boundary. A processor calculates a first effective distance between the first distribution boundary and a first centroid of a cluster. A processor assigns the first data point to the first cluster. A processor recomputes the first centroid based on the first data point and the first distribution boundary.

Abstract: A processor may receive a transistor level integrated circuit (IC) design to be modelled. The processor may determine that the transistor level IC design has a first stage and a second stage. The processor may determine a first cross-current effective capacitance of the first stage and a second cross-current effective capacitance of the second stage. The processor may then determine a cross-current effective capacitance for the transistor level IC design by accumulating the first and second cross-current effective capacitances.

Abstract: A processor may receive a transistor level integrated circuit (IC) design to be modelled. The processor may determine that the transistor level IC design has a first stage and a second stage. The processor may determine a first cross-current effective capacitance of the first stage and a second cross-current effective capacitance of the second stage. The processor may then determine a cross-current effective capacitance for the transistor level IC design by accumulating the first and second cross-current effective capacitances.

Abstract: A processor may receive a transistor level integrated circuit (IC) design to be modelled. The processor may determine that the transistor level IC design has a first stage and a second stage. The processor may determine a first cross-current effective capacitance of the first stage and a second cross-current effective capacitance of the second stage. The processor may then determine a cross-current effective capacitance for the transistor level IC design by accumulating the first and second cross-current effective capacitances.

Abstract: A processor may receive a transistor level integrated circuit (IC) design to be modelled. The processor may determine that the transistor level IC design has a first stage and a second stage. The processor may determine a first cross-current effective capacitance of the first stage and a second cross-current effective capacitance of the second stage. The processor may then determine a cross-current effective capacitance for the transistor level IC design by accumulating the first and second cross-current effective capacitances.

Abstract: A processor may receive a transistor level integrated circuit (IC) design to be modelled. The processor may determine that the transistor level IC design has a first stage and a second stage. The processor may determine a first cross-current effective capacitance of the first stage and a second cross-current effective capacitance of the second stage. The processor may then determine a cross-current effective capacitance for the transistor level IC design by accumulating the first and second cross-current effective capacitances.

Abstract: An approach is provided in which an information handling system executes multiple timing constraint sensitivity tests on a circuit model using a first signal arrival time and generates multiple test results. The information handling system compares the multiple test results with a pre-determined probability threshold and, in response to determining that an amount of test failures included in the multiple test results meets a pre-determined failure probability threshold, the information handling system computes a timing constraint sensitivity of the circuit model based upon the first signal arrival time.

Abstract: An approach is provided in which an information handling system executes multiple timing constraint sensitivity tests on a circuit model using a first signal arrival time and generates multiple test results. The information handling system compares the multiple test results with a pre-determined probability threshold and, in response to determining that an amount of test failures included in the multiple test results meets a pre-determined failure probability threshold, the information handling system computes a timing constraint sensitivity of the circuit model based upon the first signal arrival time.

Abstract: A processor may receive a transistor level integrated circuit (IC) design to be modelled. The processor may determine that the transistor level IC design has a first stage and a second stage. The processor may determine a first cross-current effective capacitance of the first stage and a second cross-current effective capacitance of the second stage. The processor may then determine a cross-current effective capacitance for the transistor level IC design by accumulating the first and second cross-current effective capacitances.

Abstract: A processor may receive a transistor level integrated circuit (IC) design to be modelled. The processor may determine that the transistor level IC design has a first stage and a second stage. The processor may determine a first cross-current effective capacitance of the first stage and a second cross-current effective capacitance of the second stage. The processor may then determine a cross-current effective capacitance for the transistor level IC design by accumulating the first and second cross-current effective capacitances.

Abstract: A processor may receive a transistor level integrated circuit (IC) design to be modelled. The processor may determine that the transistor level IC design has a first stage and a second stage. The processor may determine a first cross-current effective capacitance of the first stage and a second cross-current effective capacitance of the second stage. The processor may then determine a cross-current effective capacitance for the transistor level IC design by accumulating the first and second cross-current effective capacitances.

Abstract: An approach is provided in which an information handling system executes multiple timing constraint sensitivity tests on a circuit model using a first signal arrival time and generates multiple test results. The information handling system compares the multiple test results with a pre-determined probability threshold and, in response to determining that an amount of test failures included in the multiple test results meets a pre-determined failure probability threshold, the information handling system computes a timing constraint sensitivity of the circuit model based upon the first signal arrival time.

Abstract: An approach is provided in which an information handling system executes multiple timing constraint sensitivity tests on a circuit model using a first signal arrival time and generates multiple test results. The information handling system compares the multiple test results with a pre-determined probability threshold and, in response to determining that an amount of test failures included in the multiple test results meets a pre-determined failure probability threshold, the information handling system computes a timing constraint sensitivity of the circuit model based upon the first signal arrival time.